linux-kernel - Re: [PATCH v2 30/36] soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE

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Message-ID: <50bb8062-757a-4838-8497-55ce7555bf96@csgroup.eu>
Date: Fri, 23 Aug 2024 10:13:27 +0200
From: Christophe Leroy <christophe.leroy@...roup.eu>
To: Herve Codina <herve.codina@...tlin.com>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Qiang Zhao <qiang.zhao@....com>,
 Li Yang <leoyang.li@....com>, Mark Brown <broonie@...nel.org>
Cc: linuxppc-dev@...ts.ozlabs.org, linux-arm-kernel@...ts.infradead.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH v2 30/36] soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE_QMC



Le 08/08/2024 à 09:11, Herve Codina a écrit :
> Current code handles CPM1 version of QMC. Even if GSMRL is specific to
> the CPM1 version, the exact same purpose and format register (GUMRL) is
> present in the QUICC Engine (QE) version of QMC. Compared to the QE
> version, the values defined for the mode bitfield are different and the
> 0x0A value defined for the QMC mode is CPM1 specific.
> 
> In order to prepare the support for the QE version, rename this bitfield
> value to clearly identify it as CPM1 specific.
> 
> Signed-off-by: Herve Codina <herve.codina@...tlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@...roup.eu>

> ---
>   drivers/soc/fsl/qe/qmc.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index 63af2608c3cd..062477b7426e 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -27,7 +27,7 @@
>   #define SCC_GSMRL_ENR		BIT(5)
>   #define SCC_GSMRL_ENT		BIT(4)
>   #define SCC_GSMRL_MODE_MASK	GENMASK(3, 0)
> -#define SCC_GSMRL_MODE_QMC	FIELD_PREP_CONST(SCC_GSMRL_MODE_MASK, 0x0A)
> +#define SCC_CPM1_GSMRL_MODE_QMC	FIELD_PREP_CONST(SCC_GSMRL_MODE_MASK, 0x0A)
>   
>   /* SCC general mode register low (32 bits) */
>   #define SCC_GSMRH	0x04
> @@ -1642,7 +1642,7 @@ static int qmc_cpm1_init_scc(struct qmc *qmc)
>   	qmc_write32(qmc->scc_regs + SCC_GSMRH, val);
>   
>   	/* enable QMC mode */
> -	qmc_write32(qmc->scc_regs + SCC_GSMRL, SCC_GSMRL_MODE_QMC);
> +	qmc_write32(qmc->scc_regs + SCC_GSMRL, SCC_CPM1_GSMRL_MODE_QMC);
>   
>   	/* Disable and clear interrupts */
>   	qmc_write16(qmc->scc_regs + SCC_SCCM, 0x0000);