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Message-ID: <51965506b0b18dac7a64617838602bddac634cfd.1724748733.git.perry.yuan@amd.com> Date: Tue, 27 Aug 2024 17:36:52 +0800 From: Perry Yuan <perry.yuan@....com> To: <hdegoede@...hat.com>, <ilpo.jarvinen@...ux.intel.com>, <Mario.Limonciello@....com>, <Borislav.Petkov@....com>, <kprateek.nayak@....com> CC: <Alexander.Deucher@....com>, <Xinmei.Huang@....com>, <bharathprabhu.perdoor@....com>, <poonam.aggrwal@....com>, <Li.Meng@....com>, <platform-driver-x86@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <Xiaojian.Du@....com> Subject: [PATCH 04/11] x86/msr-index: define AMD heterogeneous CPU related MSR Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Signed-off-by: Perry Yuan <perry.yuan@....com> --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 384739d592af..141509ff9cf0 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -682,6 +682,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e -- 2.34.1
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