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Message-ID: <3rwkr4tqyki7umt75bgy6wcs2whchw2vb5ckrkqffaizxm3ssp@glkarq76vl4f>
Date: Tue, 27 Aug 2024 13:38:17 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Qiang Yu <quic_qianyu@...cinc.com>
Cc: manivannan.sadhasivam@...aro.org, vkoul@...nel.org, kishon@...nel.org,
robh@...nel.org, andersson@...nel.org, konradybcio@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, mturquette@...libre.com, sboyd@...nel.org, abel.vesa@...aro.org,
quic_msarkar@...cinc.com, quic_devipriy@...cinc.com, dmitry.baryshkov@...aro.org,
kw@...ux.com, lpieralisi@...nel.org, neil.armstrong@...aro.org,
linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH 3/8] phy: qcom: qmp: Add phy register and clk setting for
x1e80100 PCIe3
On Mon, Aug 26, 2024 at 11:36:26PM -0700, Qiang Yu wrote:
> if (cfg->tbls.ln_shrd)
> qmp->ln_shrd = base + offs->ln_shrd;
>
> @@ -4424,6 +4641,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
> }, {
> .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
> .data = &x1e80100_qmp_gen4x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy",
Undocumented compatible or your patch order is wrong.
> + .data = &x1e80100_qmp_gen4x8_pciephy_cfg,
> },
Best regards,
Krzysztof
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