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Message-ID: <20240828-gainfully-cringing-2f420d8882bd@thorsis.com>
Date: Wed, 28 Aug 2024 08:55:27 +0200
From: Alexander Dahl <ada@...rsis.com>
To: claudiu beznea <claudiu.beznea@...on.dev>
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Nicolas Ferre <nicolas.ferre@...rochip.com>
Subject: Re: get, prepare, enable a clock not in DT?
Hello Claudiu,
Am Fri, Aug 23, 2024 at 05:29:44PM +0300 schrieb claudiu beznea:
>
>
> On 20.08.2024 15:17, Alexander Dahl wrote:
> > By chance: I don't have a sama7g5 based board at hand for testing.
> > The datasheet says the same as for sam9x60.
> > Does the nvmem_microchip_otpc driver actually work without timeout on
> > sama7g5?
>
> Yes! This should be because system bus is clocked from MCK0 (as mentioned
> in peripheral identifiers table) which is enabled by bootloader.
Not sure I can follow. Citing the SAMA7G5 datasheet section 30.4
(OTPC Product Dependencies):
"The OTPC is clocked through the Power Management Controller
(PMC). The user must power on the main RC oscillator and enable
the peripheral clock of the OTPC prior to reading or writing the
OTP memory."
Table from section 8.5 (Peripheral Clocks …) has no check mark at "PMC
clock control" but indeed lists MCK0 as main system bus clock. If it
works on SAMA7G5 without explicitly enabling main RC oscillator, then
either that clock is on accidentally, or the datasheet is wrong in the
OTPC section.
Personally I find the "clocked through PMC" part in the OTPC
section suspicious, because in the peripheral identifiers table OTPC
has no "PMC Clock Control" mark.
Not sure what's the difference between SAM9X60 and SAMA7G5 internally,
though. From a user's POV it's possible one of them requires the
main RC osc, and the other does not, but currently you can't tell from
the datasheets.
> Here is a snapshot of reading the NVMEM on a SAMA7G5 with bootconfig and
> thermal calibration packets:
> https://www.linux4sam.org/bin/view/Linux4SAM/ThermalFaq
Greets
Alex
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