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Message-ID: <CAHb3i=vWNmokQYyOZJOVeaJaT6XAroct2gZiJYPVQf6rHzR5LA@mail.gmail.com>
Date: Sun, 1 Sep 2024 18:53:38 +0300
From: Tali Perry <tali.perry1@...il.com>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: Tyrone Ting <warp5tw@...il.com>, avifishman70@...il.com, tmaimon77@...il.com, 
	venture@...gle.com, yuenn@...gle.com, benjaminfair@...gle.com, 
	andi.shyti@...nel.org, wsa@...nel.org, rand.sec96@...il.com, 
	wsa+renesas@...g-engineering.com, tali.perry@...oton.com, 
	Avi.Fishman@...oton.com, tomer.maimon@...oton.com, KWLIU@...oton.com, 
	JJLIU0@...oton.com, kfting@...oton.com, openbmc@...ts.ozlabs.org, 
	linux-i2c@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 6/7] i2c: npcm: use i2c frequency table

On Fri, Aug 30, 2024 at 10:19 PM Andy Shevchenko
<andriy.shevchenko@...ux.intel.com> wrote:
>
> On Fri, Aug 30, 2024 at 11:46:39AM +0800, Tyrone Ting wrote:
> > Modify i2c frequency from table parameters
> > for NPCM i2c modules.
> >
> > Supported frequencies are:
> >
> > 1. 100KHz
> > 2. 400KHz
> > 3. 1MHz
>
> There is no explanations "why". What's wrong with the calculations done in the
> current code?
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
Hi Andy,

The original equations were tested on a variety of chips and base clocks.
Since we added devices that use higher frequencies of the module we
saw that there is a mismatch between the equation and the actual
results on the bus itself, measured on scope.
So instead of using the equations we did an optimization per module
frequency, verified on a device.
Most of the work was focused on the rise time of the SCL and SDA,
which depends on external load of the bus and PU.
We needed to make sure that in all valid range of load the rise time
is compliant of the SMB spec timing requirements.

This patch include the final values after extensive testing both at
Nuvoton as well as at customer sites.

BR,
Tali Perry
Nuvoton.

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