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Message-ID: <20240902140039.1972899-1-uwu@icenowy.me>
Date: Mon, 2 Sep 2024 22:00:39 +0800
From: Icenowy Zheng <uwu@...nowy.me>
To: Matt Coster <Matt.Coster@...tec.com>,
Frank Binns <frank.binns@...tec.com>
Cc: Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
dri-devel@...ts.freedesktop.org,
linux-kernel@...r.kernel.org,
Icenowy Zheng <uwu@...nowy.me>
Subject: [PATCH v2] drm/imagination: properly support stopping LAYOUT_MARS = 1 cores
Some new Rogue GPU cores have an extra MARS power domain, which
controlls the power of the firmware core and allows the firmware core to
power down most parts of the GPU.
Adapt to this by ignoring power domains that should be powered down by
the fiwmare and checking MARS idle status instead.
The logic mimics RGXStop() function in the DDK kernel mode source code.
Tested on BXE-4-32 (36.50.54.182) with firmware build 6503725 OS provided
by Imagination Technologies.
Signed-off-by: Icenowy Zheng <uwu@...nowy.me>
---
Changes in v2:
- Fixed some wrong change that moves the original logic into if(mars)
instead of if(!mars).
.../gpu/drm/imagination/pvr_fw_startstop.c | 48 +++++++++++++------
1 file changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
index 36cec227cfe3c..ae137e35edf3b 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
@@ -191,19 +191,27 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
~(ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN |
ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN |
ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN);
+ const u32 mars_idle_mask = ROGUE_CR_MARS_IDLE_CPU_EN |
+ ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN;
bool skip_garten_idle = false;
+ u32 mars = 0;
u32 reg_value;
int err;
+ PVR_FEATURE_VALUE(pvr_dev, layout_mars, &mars);
+
/*
* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper.
* For cores with the LAYOUT_MARS feature, SIDEKICK would have been
* powered down by the FW.
*/
- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask,
- sidekick_idle_mask, POLL_TIMEOUT_USEC);
- if (err)
- return err;
+ if (!mars) {
+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE,
+ sidekick_idle_mask,
+ sidekick_idle_mask, POLL_TIMEOUT_USEC);
+ if (err)
+ return err;
+ }
/* Unset MTS DM association with threads. */
pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC,
@@ -257,21 +265,27 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
* For cores with the LAYOUT_MARS feature, SLC would have been powered
* down by the FW.
*/
- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE,
- ROGUE_CR_SLC_IDLE_MASKFULL,
- ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC);
- if (err)
- return err;
+ if (!mars) {
+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE,
+ ROGUE_CR_SLC_IDLE_MASKFULL,
+ ROGUE_CR_SLC_IDLE_MASKFULL,
+ POLL_TIMEOUT_USEC);
+ if (err)
+ return err;
+ }
/*
* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper.
* For cores with the LAYOUT_MARS feature, SIDEKICK would have been powered
* down by the FW.
*/
- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask,
- sidekick_idle_mask, POLL_TIMEOUT_USEC);
- if (err)
- return err;
+ if (!mars) {
+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE,
+ sidekick_idle_mask,
+ sidekick_idle_mask, POLL_TIMEOUT_USEC);
+ if (err)
+ return err;
+ }
if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META) {
err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value);
@@ -287,7 +301,13 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
skip_garten_idle = true;
}
- if (!skip_garten_idle) {
+ if (mars) {
+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_MARS_IDLE,
+ mars_idle_mask, mars_idle_mask,
+ POLL_TIMEOUT_USEC);
+ if (err)
+ return err;
+ } else if (!skip_garten_idle) {
err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE,
ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
--
2.46.0
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