linux-kernel - [PATCH v2 2/3] clk: at91: clk-sam9x60-pll: increase maximum amount of plls

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Message-ID: <370cc48eeb3dbec796e17c1af9bff2c10de331bb.1725392645.git.Ryan.Wanner@microchip.com>
Date: Wed, 4 Sep 2024 08:54:12 -0700
From: <Ryan.Wanner@...rochip.com>
To: <mturquette@...libre.com>, <sboyd@...nel.org>,
	<nicolas.ferre@...rochip.com>, <alexandre.belloni@...tlin.com>,
	<claudiu.beznea@...on.dev>
CC: <varshini.rajendran@...rochip.com>, <linux-kernel@...r.kernel.org>,
	<linux-clk@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, "Ryan
 Wanner" <Ryan.Wanner@...rochip.com>
Subject: [PATCH v2 2/3] clk: at91: clk-sam9x60-pll: increase maximum amount of plls

From: Ryan Wanner <Ryan.Wanner@...rochip.com>

Increase maximum amount of PLLs to 9 to support SAMA7D65 SoC PLL
requirements.

Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>
---
 drivers/clk/at91/clk-sam9x60-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index fda041102224..cefd9948e103 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -23,7 +23,7 @@
 #define UPLL_DIV		2
 #define PLL_MUL_MAX		(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
 
-#define PLL_MAX_ID		7
+#define PLL_MAX_ID		9
 
 struct sam9x60_pll_core {
 	struct regmap *regmap;
-- 
2.43.0