linux-kernel - Re: [PATCH V3 1/6] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy

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Message-ID: <de17d37f-ed0c-4e73-91d5-fc902573212a@quicinc.com>
Date: Wed, 4 Sep 2024 22:50:17 +0530
From: Sricharan Ramabadhran <quic_srichara@...cinc.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
CC: <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
        <manivannan.sadhasivam@...aro.org>, <robh@...nel.org>,
        <krzk+dt@...nel.org>, <conor+dt@...nel.org>, <vkoul@...nel.org>,
        <kishon@...nel.org>, <andersson@...nel.org>, <konradybcio@...nel.org>,
        <p.zabel@...gutronix.de>, <dmitry.baryshkov@...aro.org>,
        <quic_nsekar@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
        <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
        <robimarko@...il.com>
Subject: Re: [PATCH V3 1/6] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe
 uniphy



On 8/30/2024 1:53 PM, Krzysztof Kozlowski wrote:
> On Fri, Aug 30, 2024 at 01:41:27PM +0530, Sricharan R wrote:
>> From: Nitheesh Sekar <quic_nsekar@...cinc.com>
>>
>> Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5018.
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>> Signed-off-by: Nitheesh Sekar <quic_nsekar@...cinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
>> ---
>>   [v3] Added reviewed-by tags
>>
>>   .../phy/qcom,ipq5018-uniphy-pcie.yaml         | 70 +++++++++++++++++++
>>   1 file changed, 70 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
>> new file mode 100644
>> index 000000000000..c04dd179eb8b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
>> @@ -0,0 +1,70 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/qcom,ipq5018-uniphy-pcie.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm UNIPHY PCIe 28LP PHY controller for genx1, genx2
>> +
>> +maintainers:
>> +  - Nitheesh Sekar <quic_nsekar@...cinc.com>
>> +  - Sricharan Ramabadhran <quic_srichara@...cinc.com>
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - qcom,ipq5018-uniphy-pcie-gen2x1
>> +      - qcom,ipq5018-uniphy-pcie-gen2x2
> 
> ... and now I wonder why there are two compatibles. Isn't the phy the
> same? We talk about the same hardware?
  We have 2 different physical phys. One with single lane and another
  with dual lane. Its same IP, but for 2 lanes, 2 sets of the phy
  specific registers needs to configured. So differentiating that here.

Regards,
  Sricharan