linux-kernel - [PATCH 0/2] Disable 32-bit EL0 for Apple A10(X), T2

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Message-ID: <20240906170648.323759-1-towinchenmi@gmail.com>
Date: Sat,  7 Sep 2024 00:59:37 +0800
From: Nick Chan <towinchenmi@...il.com>
To: Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will@...nel.org>,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Cc: asahi@...r.kernel.org,
	~postmarketos/upstreaming@...ts.sr.ht,
	Nick Chan <towinchenmi@...il.com>
Subject: [PATCH 0/2] Disable 32-bit EL0 for Apple A10(X), T2

Hi,

Apple's A10(X), T2 SoCs consists of pairs of performance and efficiency
cores. However, only one of the core types may be active at a given time,
and to software, it appears as logical cores that could switch between
P-mode and E-mode, depending on the p-state.

Unforunately, only the performance cores can execute 32-bit EL0. To
software, this results in logical cores that lose ability to execute
32-bit EL0 when the p-state is below a certain value.

Since these CPU cores only supported 16K pages, many AArch32
executables will not run anyways. This series disables 32-bit EL0 for
these SoCs.

Nick Chan

---

Nick Chan (2):
  arm64: cputype: Add CPU types for A7-A11, T2 SoCs
  arm64: cpufeature: Pretend that Apple A10(X), T2 does not support
    32-bit EL0

 arch/arm64/include/asm/cputype.h | 42 +++++++++++++++++++++++---------
 arch/arm64/kernel/cpufeature.c   | 25 +++++++++++++++++++
 2 files changed, 55 insertions(+), 12 deletions(-)

base-commit: 9aaeb87ce1e966169a57f53a02ba05b30880ffb8
-- 
2.46.0