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Message-ID: <20240906121308.5013-5-suravee.suthikulpanit@amd.com> Date: Fri, 6 Sep 2024 12:13:07 +0000 From: Suravee Suthikulpanit <suravee.suthikulpanit@....com> To: <linux-kernel@...r.kernel.org>, <iommu@...ts.linux.dev> CC: <joro@...tes.org>, <robin.murphy@....com>, <vasant.hegde@....com>, <ubizjak@...il.com>, <jgg@...dia.com>, <jon.grimm@....com>, <santosh.shukla@....com>, <pandoh@...gle.com>, <kumaranand@...gle.com>, Suravee Suthikulpanit <suravee.suthikulpanit@....com> Subject: [PATCH v3 4/5] iommu/amd: Modify clear_dte_entry() to avoid in-place update Lock DTE and copy value to a temporary storage before update using cmpxchg128. Also, refactor the function to simplify logic for applying erratum 63. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@....com> --- drivers/iommu/amd/amd_iommu_types.h | 2 ++ drivers/iommu/amd/iommu.c | 27 ++++++++++++++++++++------- 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 1836da2d9e60..81a994471a30 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -425,6 +425,8 @@ #define DTE_GPT_LEVEL_SHIFT 54 +#define DTE_SYSMGT_MASK GENMASK_ULL(41, 40) + #define GCR3_VALID 0x01ULL #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index f18ae6c077f4..15eb816d4313 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2025,19 +2025,32 @@ static void set_dte_entry(struct amd_iommu *iommu, } } -static void clear_dte_entry(struct amd_iommu *iommu, u16 devid) +static void clear_dte_entry(struct amd_iommu *iommu, struct iommu_dev_data *dev_data) { - struct dev_table_entry *dev_table = get_dev_table(iommu); + struct dev_table_entry new; + struct dev_table_entry *dte = &get_dev_table(iommu)[dev_data->devid]; + + /* + * Need to preserve DTE[96:106] because certain fields are + * programmed using value in IVRS table from early init phase. + */ + spin_lock(&dev_data->dte_lock); + get_dte256(iommu, dev_data, &new); /* remove entry from the device table seen by the hardware */ - dev_table[devid].data[0] = DTE_FLAG_V; + new.data[0] = DTE_FLAG_V; if (!amd_iommu_snp_en) - dev_table[devid].data[0] |= DTE_FLAG_TV; + new.data[0] |= DTE_FLAG_TV; - dev_table[devid].data[1] &= DTE_FLAG_MASK; + new.data[1] &= DTE_FLAG_MASK; - amd_iommu_apply_erratum_63(iommu, devid); + /* Apply erratum 63 */ + if (FIELD_GET(DTE_SYSMGT_MASK, new.data[1]) == 0x01) + new.data[0] |= BIT_ULL(DEV_ENTRY_IW); + + WARN_ON(!try_cmpxchg128(&dte->data128[0], &dte->data128[0], new.data128[0])); + spin_unlock(&dev_data->dte_lock); } /* Update and flush DTE for the given device */ @@ -2048,7 +2061,7 @@ void amd_iommu_dev_update_dte(struct iommu_dev_data *dev_data, bool set) if (set) set_dte_entry(iommu, dev_data); else - clear_dte_entry(iommu, dev_data->devid); + clear_dte_entry(iommu, dev_data); clone_aliases(iommu, dev_data->dev); device_flush_dte(dev_data); -- 2.34.1
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