| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAAhV-H4B19+pybM_PeSNEnSmWaLLi6W15t2scbKhEOGLyCtEWw@mail.gmail.com>
Date: Sun, 8 Sep 2024 10:40:51 +0800
From: Huacai Chen <chenhuacai@...nel.org>
To: Jiaxun Yang <jiaxun.yang@...goat.com>
Cc: WANG Xuerui <kernel@...0n.name>, "Rafael J. Wysocki" <rafael@...nel.org>,
Viresh Kumar <viresh.kumar@...aro.org>, Thomas Gleixner <tglx@...utronix.de>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>, loongarch@...ts.linux.dev,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
linux-mips@...r.kernel.org, kvm@...r.kernel.org
Subject: Re: [PATCH 2/5] LoongArch: Probe more CPU features from CPUCFG
Hi, Jiaxun,
On Sat, Sep 7, 2024 at 6:17 PM Jiaxun Yang <jiaxun.yang@...goat.com> wrote:
>
> Probe ISA level, TLB, IOCSR information from CPUCFG to
> improve kernel resilience to different core implementations.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com>
> ---
> arch/loongarch/include/asm/cpu.h | 2 +-
> arch/loongarch/kernel/cpu-probe.c | 47 ++++++++++++++++++++++++++-------------
> 2 files changed, 32 insertions(+), 17 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/cpu.h
> index 7c44f4ede3a2..31a2de821236 100644
> --- a/arch/loongarch/include/asm/cpu.h
> +++ b/arch/loongarch/include/asm/cpu.h
> @@ -86,7 +86,7 @@ enum cpu_type_enum {
> #define CPU_FEATURE_LBT_ARM 11 /* CPU has ARM Binary Translation */
> #define CPU_FEATURE_LBT_MIPS 12 /* CPU has MIPS Binary Translation */
> #define CPU_FEATURE_TLB 13 /* CPU has TLB */
> -#define CPU_FEATURE_CSR 14 /* CPU has CSR */
> +#define CPU_FEATURE_IOCSR 14 /* CPU has IOCSR */
> #define CPU_FEATURE_WATCH 15 /* CPU has watchpoint registers */
> #define CPU_FEATURE_VINT 16 /* CPU has vectored interrupts */
> #define CPU_FEATURE_CSRIPI 17 /* CPU has CSR-IPI */
> diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
> index 4446616d497c..6a82ceb6e321 100644
> --- a/arch/loongarch/kernel/cpu-probe.c
> +++ b/arch/loongarch/kernel/cpu-probe.c
> @@ -91,12 +91,23 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
> unsigned int config;
> unsigned long asid_mask;
>
> - c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_IOCSR |
> - LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH;
> + c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_VINT |
> + LOONGARCH_CPU_WATCH;
>
> elf_hwcap = HWCAP_LOONGARCH_CPUCFG;
>
> config = read_cpucfg(LOONGARCH_CPUCFG1);
> +
> + if (config & CPUCFG1_ISGR64)
> + set_isa(c, LOONGARCH_CPU_ISA_LA64);
> + else if (config & CPUCFG1_ISGR32)
> + set_isa(c, LOONGARCH_CPU_ISA_LA32S);
> + else
> + set_isa(c, LOONGARCH_CPU_ISA_LA32R);
Switch-case is better than if-else here.
> + if (config & CPUCFG1_PAGING)
> + c->options |= LOONGARCH_CPU_TLB;
> + if (config & CPUCFG1_IOCSR)
> + c->options |= LOONGARCH_CPU_IOCSR;
> if (config & CPUCFG1_UAL) {
> c->options |= LOONGARCH_CPU_UAL;
> elf_hwcap |= HWCAP_LOONGARCH_UAL;
> @@ -222,6 +233,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int
> {
> uint64_t *vendor = (void *)(&cpu_full_name[VENDOR_OFFSET]);
> uint64_t *cpuname = (void *)(&cpu_full_name[CPUNAME_OFFSET]);
> + const char *core_name = "Unknown";
>
> if (!__cpu_full_name[cpu])
> __cpu_full_name[cpu] = cpu_full_name;
> @@ -232,40 +244,43 @@ static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int
> switch (c->processor_id & PRID_SERIES_MASK) {
> case PRID_SERIES_LA132:
> c->cputype = CPU_LOONGSON32;
> - set_isa(c, LOONGARCH_CPU_ISA_LA32S);
> __cpu_family[cpu] = "Loongson-32bit";
> - pr_info("32-bit Loongson Processor probed (LA132 Core)\n");
> + core_name = "LA132";
> break;
> case PRID_SERIES_LA264:
> c->cputype = CPU_LOONGSON64;
> - set_isa(c, LOONGARCH_CPU_ISA_LA64);
> __cpu_family[cpu] = "Loongson-64bit";
> - pr_info("64-bit Loongson Processor probed (LA264 Core)\n");
> + core_name = "LA264";
> break;
> case PRID_SERIES_LA364:
> c->cputype = CPU_LOONGSON64;
> - set_isa(c, LOONGARCH_CPU_ISA_LA64);
> __cpu_family[cpu] = "Loongson-64bit";
> - pr_info("64-bit Loongson Processor probed (LA364 Core)\n");
> + core_name = "LA364";
> break;
> case PRID_SERIES_LA464:
> c->cputype = CPU_LOONGSON64;
> - set_isa(c, LOONGARCH_CPU_ISA_LA64);
> __cpu_family[cpu] = "Loongson-64bit";
> - pr_info("64-bit Loongson Processor probed (LA464 Core)\n");
> + core_name = "LA464";
> break;
> case PRID_SERIES_LA664:
> c->cputype = CPU_LOONGSON64;
> - set_isa(c, LOONGARCH_CPU_ISA_LA64);
> __cpu_family[cpu] = "Loongson-64bit";
> - pr_info("64-bit Loongson Processor probed (LA664 Core)\n");
> + core_name = "LA664";
> break;
> default: /* Default to 64 bit */
> - c->cputype = CPU_LOONGSON64;
> - set_isa(c, LOONGARCH_CPU_ISA_LA64);
> - __cpu_family[cpu] = "Loongson-64bit";
> - pr_info("64-bit Loongson Processor probed (Unknown Core)\n");
> + if (c->isa_level & LOONGARCH_CPU_ISA_LA64) {
> + c->cputype = CPU_LOONGSON64;
> + __cpu_family[cpu] = "Loongson-64bit";
> + } else if (c->isa_level & LOONGARCH_CPU_ISA_LA32S) {
> + c->cputype = CPU_LOONGSON32;
> + __cpu_family[cpu] = "Loongson-32bit";
Change the name to "Loongson-32bit Standard".
Huacai
> + } else if (c->isa_level & LOONGARCH_CPU_ISA_LA32R) {
> + c->cputype = CPU_LOONGSON32;
> + __cpu_family[cpu] = "Loongson-32bit Reduced";
> + }
> }
> +
> + pr_info("%s Processor probed (%s Core)\n", __cpu_family[cpu], core_name);
> }
>
> #ifdef CONFIG_64BIT
>
> --
> 2.46.0
>
Powered by blists - more mailing lists