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Message-ID: <86zfog6jrv.wl-maz@kernel.org>
Date: Tue, 10 Sep 2024 08:38:12 +0100
From: Marc Zyngier <maz@...nel.org>
To: Sergey Shtylyov <s.shtylyov@....ru>
Cc: Thomas Gleixner <tglx@...utronix.de>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] irqchip/gic: prevent buffer overflow in gic_ipi_send_mask()
On Mon, 09 Sep 2024 20:48:24 +0100,
Sergey Shtylyov <s.shtylyov@....ru> wrote:
>
> GICv2 spec does talk about 1-N and N-N interrupt handling modes;
> at the same time, I can't find such words in the GICv3/4 spec. :-)
See 1.2.3 "Models for handling interrupts" and the pointers this
section contains. The major difference is that 1:N is enabled on a
per-CPU basis instead of a per interrupt basis. Needless to say, Linux
doesn't support this, although I've been pondering it at times.
M.
--
Without deviation from the norm, progress is not possible.
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