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Message-Id: <20240911-pci-qcom-gen4-stability-v7-0-743f5c1fd027@linaro.org>
Date: Wed, 11 Sep 2024 20:56:25 +0530
From: Manivannan Sadhasivam via B4 Relay <devnull+manivannan.sadhasivam.linaro.org@...nel.org>
To: Richard Zhu <hongxing.zhu@....com>,
Lucas Stach <l.stach@...gutronix.de>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, Jingoo Han <jingoohan1@...il.com>,
Chuanhua Lei <lchuanhua@...linear.com>,
Marek Vasut <marek.vasut+renesas@...il.com>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
Pratyush Anand <pratyush.anand@...il.com>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>
Cc: linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
imx@...ts.linux.dev, linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, linux-arm-msm@...r.kernel.org,
abel.vesa@...aro.org, johan+linaro@...nel.org,
Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>,
linux-tegra@...r.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Frank Li <Frank.Li@....com>
Subject: [PATCH v7 0/4] PCI: qcom: Add 16.0 GT/s equalization and margining
settings
Hi,
This series adds 16.0 GT/s specific equalization and RX lane margining settings
to the Qcom RC and EP drivers. This series is mandatory for the stable operation
of the PCIe link at 16.0 GT/s on the Qcom platforms.
NOTE:
=====
I've taken over the series from Shashank based on the discussion [1]. In order
to apply the equalization/margining settings properly in the Qcom driver, I
added the first 2 patches to the series which inevitably touches other vendor
drivers also.
- Mani
Changes in v7:
- Fixed the build issue reported by Kbuild bot in patch 1/4
- Changed the logic to check invalid max_link_speed in patch 2/4
- Cleanups to patches 3/4 and 4/4 as suggested by Johan
- Added include header guard to pci-qcom-common.h
- Link to v6: https://lore.kernel.org/r/20240904-pci-qcom-gen4-stability-v6-0-ec39f7ae3f62@linaro.org
Changes in v6:
- Dropped the code refactoring patch as suggested by Johan
- Added 2 patches to fix the caching of maximum supported link speed value that
is needed to apply the equalization/margining settings
- Updated the commit message of patch 3 as per Bjorn's suggestion
For previous changelogs, please refer [2]
[1] https://lore.kernel.org/linux-pci/af65b744-7538-4929-9ab4-8ee42e17b8d1@quicinc.com/
[2] https://lore.kernel.org/linux-pci/20240821170917.21018-1-quic_schintav@quicinc.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
---
Manivannan Sadhasivam (2):
PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
Shashank Babu Chinta Venkata (2):
PCI: qcom: Add equalization settings for 16.0 GT/s
PCI: qcom: Add RX lane margining settings for 16.0 GT/s
MAINTAINERS | 4 +-
drivers/pci/controller/dwc/Kconfig | 5 ++
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pci-imx6.c | 8 +--
drivers/pci/controller/dwc/pcie-designware.c | 22 +++++---
drivers/pci/controller/dwc/pcie-designware.h | 33 +++++++++++-
drivers/pci/controller/dwc/pcie-intel-gw.c | 4 +-
drivers/pci/controller/dwc/pcie-qcom-common.c | 78 +++++++++++++++++++++++++++
drivers/pci/controller/dwc/pcie-qcom-common.h | 14 +++++
drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +++
drivers/pci/controller/dwc/pcie-qcom.c | 6 +++
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 6 +--
drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +-
drivers/pci/controller/dwc/pcie-tegra194.c | 19 +++----
14 files changed, 178 insertions(+), 30 deletions(-)
---
base-commit: 47ac09b91befbb6a235ab620c32af719f8208399
change-id: 20240904-pci-qcom-gen4-stability-02ec65a7e6e4
Best regards,
--
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
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