linux-kernel - RE: [PATCH 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5 controller-1.

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID:
 <SN7PR12MB7201112E057B779EFCAB4E898B9B2@SN7PR12MB7201.namprd12.prod.outlook.com>
Date: Wed, 11 Sep 2024 04:54:13 +0000
From: "Havalige, Thippeswamy" <thippeswamy.havalige@....com>
To: Krzysztof Kozlowski <krzk@...nel.org>, "manivannan.sadhasivam@...aro.org"
	<manivannan.sadhasivam@...aro.org>, "robh@...nel.org" <robh@...nel.org>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
	"conor+dt@...nel.org" <conor+dt@...nel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>
CC: "Gogada, Bharat Kumar" <bharat.kumar.gogada@....com>, "Simek, Michal"
	<michal.simek@....com>, "lpieralisi@...nel.org" <lpieralisi@...nel.org>,
	"kw@...ux.com" <kw@...ux.com>
Subject: RE: [PATCH 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible string
 for CPM5 controller-1.

Hi Krzysztof,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@...nel.org>
> Sent: Friday, September 6, 2024 5:49 PM
> To: Havalige, Thippeswamy <thippeswamy.havalige@....com>;
> manivannan.sadhasivam@...aro.org; robh@...nel.org; linux-
> pci@...r.kernel.org; bhelgaas@...gle.com; linux-arm-
> kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
> krzk+dt@...nel.org; conor+dt@...nel.org; devicetree@...r.kernel.org
> Cc: Gogada, Bharat Kumar <bharat.kumar.gogada@....com>; Simek,
> Michal <michal.simek@....com>; lpieralisi@...nel.org; kw@...ux.com
> Subject: Re: [PATCH 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible string
> for CPM5 controller-1.
> 
> On 06/09/2024 12:50, Havalige, Thippeswamy wrote:
> > Hi Krzysztof,
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@...nel.org>
> >> Sent: Friday, September 6, 2024 4:16 PM
> >> To: Havalige, Thippeswamy <thippeswamy.havalige@....com>;
> >> manivannan.sadhasivam@...aro.org; robh@...nel.org; linux-
> >> pci@...r.kernel.org; bhelgaas@...gle.com; linux-arm-
> >> kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
> >> krzk+dt@...nel.org; conor+dt@...nel.org; devicetree@...r.kernel.org
> >> Cc: Gogada, Bharat Kumar <bharat.kumar.gogada@....com>; Simek,
> >> Michal <michal.simek@....com>; lpieralisi@...nel.org; kw@...ux.com
> >> Subject: Re: [PATCH 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible
> string
> >> for CPM5 controller-1.
> >>
> >> On 06/09/2024 12:43, Havalige, Thippeswamy wrote:
> >>> Hi Krzysztof
> >>>
> >>>> -----Original Message-----
> >>>> From: Krzysztof Kozlowski <krzk@...nel.org>
> >>>> Sent: Friday, September 6, 2024 3:26 PM
> >>>> To: Havalige, Thippeswamy <thippeswamy.havalige@....com>;
> >>>> manivannan.sadhasivam@...aro.org; robh@...nel.org; linux-
> >>>> pci@...r.kernel.org; bhelgaas@...gle.com; linux-arm-
> >>>> kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
> >>>> krzk+dt@...nel.org; conor+dt@...nel.org; devicetree@...r.kernel.org
> >>>> Cc: Gogada, Bharat Kumar <bharat.kumar.gogada@....com>; Simek,
> >> Michal
> >>>> <michal.simek@....com>; lpieralisi@...nel.org; kw@...ux.com
> >>>> Subject: Re: [PATCH 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible
> >>>> string for CPM5 controller-1.
> >>>>
> >>>> On 06/09/2024 11:31, Thippeswamy Havalige wrote:
> >>>>> The Xilinx Versal premium series has CPM5 block which supports two
> >>>>> typeA Root Port controller functionality at Gen5 speed.
> >>>>>
> >>>>> Add compatible string to distinguish between two CPM5 rootport
> >>>> controller1.
> >>>>
> >>>> Subjects NEVER end with full stops.
> >>> Thanks, Update in the next patch series.
> >>>>>
> >>>>> Error interrupt register and bits for both the controllers are at
> >>>>> different.
> >>>>>
> >>>>> Signed-off-by: Thippeswamy Havalige <thippesw@....com>
> >>>>> ---
> >>>>>  Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 1 +
> >>>>>  1 file changed, 1 insertion(+)
> >>>>>
> >>>>> diff --git
> >>>>> a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> >>>>> b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> >>>>> index 989fb0fa2577..b63a759ec2d7 100644
> >>>>> --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> >>>>> +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> >>>>> @@ -17,6 +17,7 @@ properties:
> >>>>>      enum:
> >>>>>        - xlnx,versal-cpm-host-1.00
> >>>>>        - xlnx,versal-cpm5-host
> >>>>> +      - xlnx,versal-cpm5-host1
> >>>>
> >>>> That's poor naming. "-1.00" and now "1". Get your naming
> reasonable...
> >>> Here 1.00 represents the IP versioning and host1 represents controller-
> 1.
> >>
> >> I understand but you repeating the same is not helping. Make it better
> and
> >> next time upstream "host1-1" compatible.
> >>
> >> Number of ports, BTW, comes from ports, right? So no need for the
> >> compatible.
> >
> > To differentiate between the registers for Controller-0 and Controller-1, I
> am utilizing a compatible string in the driver. This approach enables the
> driver to identify and manage the registers associated with each controller
> based on the specified compatible string.
> >
> 
> Please don't state the obvious... I know how Linux kernel works. But
> maybe I wasn't clear - do you have ports property there? I guess not, as
> it is PCI.
> 
> What I claim here, is that you have exactly the same hardware. Same
> hardware, same compatible.


Apologies for the misunderstanding. You're correct—the ports property is not applicable
to PCI devices.
Based on Bjorn's input, I'll follow the recommended process for handling this scenario.
Thank you for the clarification.

> Best regards,
> Krzysztof