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Message-ID: <20240912162440.be23sgv5v5ojtf3q@desk>
Date: Thu, 12 Sep 2024 09:24:40 -0700
From: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
To: Jon Kohler <jon@...anix.com>
Cc: Thomas Gleixner <tglx@...utronix.de>, Borislav Petkov <bp@...en8.de>,
Peter Zijlstra <peterz@...radead.org>,
Josh Poimboeuf <jpoimboe@...nel.org>,
Ingo Molnar <mingo@...hat.com>,
Dave Hansen <dave.hansen@...ux.intel.com>, X86 ML <x86@...nel.org>,
"H. Peter Anvin" <hpa@...or.com>,
LKML <linux-kernel@...r.kernel.org>,
"kvm @ vger . kernel . org" <kvm@...r.kernel.org>,
chao.gao@...el.com
Subject: Re: [PATCH] x86/bhi: avoid hardware mitigation for
'spectre_bhi=vmexit'
On Thu, Sep 12, 2024 at 03:44:38PM +0000, Jon Kohler wrote:
> > It is only worth implementing the long sequence in VMEXIT_ONLY mode if it is
> > significantly better than toggling the MSR.
>
> Thanks for the pointer! I hadn’t seen that second sequence. I’ll do measurements on
> three cases and come back with data from an SPR system.
> 1. as-is (wrmsr on entry and exit)
> 2. Short sequence (as a baseline)
> 3. Long sequence
I wonder if virtual SPEC_CTRL feature introduced in below series can
provide speedup, as it can replace the MSR toggling with faster VMCS
operations:
https://lore.kernel.org/kvm/20240410143446.797262-1-chao.gao@intel.com/
Adding Chao for their opinion.
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