linux-kernel - Re: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <cde5eba7-770c-4521-8539-cecd69cc1db9@lunn.ch>
Date: Thu, 12 Sep 2024 21:37:48 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Ronnie.Kunin@...rochip.com
Cc: Raju.Lakkaraju@...rochip.com, netdev@...r.kernel.org,
	davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
	pabeni@...hat.com, Bryan.Whitehead@...rochip.com,
	UNGLinuxDriver@...rochip.com, linux@...linux.org.uk,
	maxime.chevallier@...tlin.com, rdunlap@...radead.org,
	Steen.Hegelund@...rochip.com, Daniel.Machon@...rochip.com,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs

> > But where is the PCS connected?
> 
> For SGMII/BASE-X support the PCI11010 uses Synopsys IP which is all internal to the device. The registers of this Synopsys block are accessible indirectly using a couple of registers (called SGMII_ACCESS and SGMII_DATA) that are mapped into the PCI11010 PCIe BAR.

Right, so not actually on the MDIO bus. Hence it is not correct to
replace the true MDIO access functions with these that do MMIO.

I do understand wanting this to look like an MDIO bus, that is what
the Synopsys driver expects. So create an MDIO bus for it. A bus of
its own.

Just for my understanding. The configuration is purely EEPROM, not
fuses? The PCS exists independent of the 'RGMII/not RGMII' bit in the
EEPROM. So you could unconditionally create the PCS MDIO bus, and
instantiate the PCS driver. In the RGMII case it would just sit there
idle. In the 'not RGMII' mode, the PCS could be used to connect to an
external PHY using SGMII or 2500BaseX. Or it could be connected to an
SFP cage, using SGMII, 1000BaseX or 2500BaseX. In both cases, you tell
phylink about it, phylink will tell you how to configure it.

	  Andrew