[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <e2d7ed77-827b-4b7c-800c-9c8f3bcb6b5a@wanadoo.fr>
Date: Fri, 13 Sep 2024 16:56:42 +0200
From: Christophe JAILLET <christophe.jaillet@...adoo.fr>
To: WangYuli <wangyuli@...ontech.com>, stable@...r.kernel.org,
gregkh@...uxfoundation.org, sashal@...nel.org, william.qiu@...rfivetech.com,
emil.renner.berthing@...onical.com, conor.dooley@...rochip.com,
xingyu.wu@...rfivetech.com, walker.chen@...rfivetech.com, robh@...nel.org,
hal.feng@...rfivetech.com
Cc: kernel@...il.dk, robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org, paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
richardcochran@...il.com, netdev@...r.kernel.org
Subject: Re: [PATCH 6.6 v2 1/4] riscv: dts: starfive: add assigned-clock* to
limit frquency
Le 12/09/2024 à 04:55, WangYuli a écrit :
> From: William Qiu <william.qiu@...rfivetech.com>
>
> [ Upstream commit af571133f7ae028ec9b5fdab78f483af13bf28d3 ]
>
> In JH7110 SoC, we need to go by-pass mode, so we need add the
> assigned-clock* properties to limit clock frquency.
>
> Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@...onical.com>
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> Signed-off-by: WangYuli <wangyuli@...ontech.com>
> ---
Hi,
if/when resent, there is a typo in the subject: s/frquency/frequency/
CJ
> .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 062b97c6e7df..4874e3bb42ab 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -204,6 +204,8 @@ &i2c6 {
>
> &mmc0 {
> max-frequency = <100000000>;
> + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> + assigned-clock-rates = <50000000>;
> bus-width = <8>;
> cap-mmc-highspeed;
> mmc-ddr-1_8v;
> @@ -220,6 +222,8 @@ &mmc0 {
>
> &mmc1 {
> max-frequency = <100000000>;
> + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> + assigned-clock-rates = <50000000>;
> bus-width = <4>;
> no-sdio;
> no-mmc;
Powered by blists - more mailing lists