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Message-ID: <jsiriw6kumswijb6wxdcjqnq3tdu524hveh7dezqdzutduvt2d@5xcdjwd6aj3f>
Date: Sat, 14 Sep 2024 22:08:33 +0300
From: Serge Semin <fancer.lancer@...il.com>
To: Andy Shevchenko <andy.shevchenko@...il.com>,
Ferry Toth <ftoth@...londelft.nl>
Cc: Viresh Kumar <vireshk@...nel.org>, Vinod Koul <vkoul@...nel.org>,
Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>, dmaengine@...r.kernel.org, linux-serial@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH RESEND v4 0/6] dmaengine: dw: Fix src/dst addr width
misconfig
On Sat, Sep 14, 2024 at 10:06:16PM +0300, Serge Semin wrote:
> Hi Andy
>
> On Sat, Sep 14, 2024 at 09:50:48PM +0300, Andy Shevchenko wrote:
> > On Mon, Aug 05, 2024 at 03:25:35PM +0300, Serge Semin wrote:
> > > On Sat, Aug 03, 2024 at 09:29:54PM +0200, Andy Shevchenko wrote:
> > > > On Fri, Aug 2, 2024 at 9:51 AM Serge Semin <fancer.lancer@...il.com> wrote:
> > > > >
> > > > > The main goal of this series is to fix the data disappearance in case of
> > > > > the DW UART handled by the DW AHB DMA engine. The problem happens on a
> > > > > portion of the data received when the pre-initialized DEV_TO_MEM
> > > > > DMA-transfer is paused and then disabled. The data just hangs up in the
> > > > > DMA-engine FIFO and isn't flushed out to the memory on the DMA-channel
> > > > > suspension (see the second commit log for details). On a way to find the
> > > > > denoted problem fix it was discovered that the driver doesn't verify the
> > > > > peripheral device address width specified by a client driver, which in its
> > > > > turn if unsupported or undefined value passed may cause DMA-transfer being
> > > > > misconfigured. It's fixed in the first patch of the series.
> > > > >
> > > > > In addition to that three cleanup patches follow the fixes described above
> > > > > in order to make the DWC-engine configuration procedure more coherent.
> > > > > First one simplifies the CTL_LO register setup methods. Second and third
> > > > > patches simplify the max-burst calculation procedure and unify it with the
> > > > > rest of the verification methods. Please see the patches log for more
> > > > > details.
> > > > >
> > > > > Final patch is another cleanup which unifies the status variables naming
> > > > > in the driver.
> > > >
> > > > Acked-by: Andy Shevchenko <andy@...nel.org>
> > >
> > > Awesome! Thanks.
> >
> > Not really :-)
> > This series broke iDMA32 + SPI PXA2xx on Intel Merrifield.
>
> Damn. Sorry to hear that.(
>
> > I haven't
> > had time to investigate further, but rolling back all patches helps.
> >
> > +Cc: Ferry who might also test and maybe investigate as he reported the
> > issue to me initially.
>
> Ferry, could you please roll back the series patch-by-patch to find
> out the particular commit to blame?
Plus to that it would be nice to have some log/info/details/etc about
what exactly is happening.
-Serge(y)
>
> -Serge(y)
>
> >
> > --
> > With Best Regards,
> > Andy Shevchenko
> >
> >
> >
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