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Message-ID: <273c175a-f640-456b-991b-15a332147540@amd.com>
Date: Mon, 16 Sep 2024 16:08:29 -0500
From: Wei Huang <wei.huang2@....com>
To: Bjorn Helgaas <helgaas@...nel.org>
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Subject: Re: [PATCH V4 02/12] PCI: Add TPH related register definition
On 9/5/24 11:41 AM, Bjorn Helgaas wrote:
> On Thu, Sep 05, 2024 at 10:08:33AM -0500, Wei Huang wrote:
>> On 9/4/24 14:52, Bjorn Helgaas wrote:
>>> I think these modes should all include "ST" to clearly delineate
>>> Steering Tags from the Processing Hints. E.g.,
>>>
>>> PCI_TPH_CAP_ST_NO_ST or maybe PCI_TPH_CAP_ST_NONE
>>
>> Can I keep "NO_ST" instead of switching over to "ST_NONE"? First, it
>> matches with PCIe spec. Secondly, IMO "ST_NONE" implies no ST support at
>> all.
>
> Sure. Does PCI_TPH_CAP_ST_NO_ST work for you? That follows the same
> PCI_TPH_CAP_ST_* pattern as below.
So I tweaked a bit in V5 to make them look cleaner: instead of ST_NO_ST,
V5 has ST_NS. Similar pattern applies to other modes:
PCI_TPH_CAP_NO_ST => PCI_TPH_CAP_ST_NS
PCI_TPH_CAP_INT_VEC => PCI_TPH_CAP_ST_IV
PCI_TPH_CAP_DEV_SPEC => PCI_TPH_CAP_ST_DS
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