lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <982ec9f3-13de-4693-b13c-fcf820ada662@kernel.org>
Date: Mon, 16 Sep 2024 21:49:45 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Nick Chan <towinchenmi@...il.com>
Cc: Hector Martin <marcan@...can.st>, Sven Peter <sven@...npeter.dev>,
 Alyssa Rosenzweig <alyssa@...enzweig.io>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, "Rafael J . Wysocki" <rafael@...nel.org>,
 Viresh Kumar <viresh.kumar@...aro.org>,
 Linus Walleij <linus.walleij@...aro.org>,
 Wim Van Sebroeck <wim@...ux-watchdog.org>, Guenter Roeck
 <linux@...ck-us.net>, Catalin Marinas <catalin.marinas@....com>,
 Will Deacon <will@...nel.org>, Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Mark Kettenis <kettenis@...nbsd.org>, asahi@...ts.linux.dev,
 linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
 linux-gpio@...r.kernel.org, linux-watchdog@...r.kernel.org,
 Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>,
 Konrad Dybcio <konradybcio@...nel.org>
Subject: Re: [PATCH v3 01/20] dt-bindings: arm: cpus: Add Apple A7-A11 CPU
 cores

On 16/09/2024 16:47, Nick Chan wrote:
> 
> 
> On 16/9/2024 22:34, Krzysztof Kozlowski wrote:
>> On Sun, Sep 15, 2024 at 03:58:46PM +0800, Nick Chan wrote:
>>> Add the following CPU cores:
>>>
>>> - apple,cyclone: A7 cores
>>> - apple,typhoon: A8 cores
>>> - apple,twister: A9 cores
>>> - apple,hurricane-zephyr: A10 logical cores
>>> - apple,monsoon: A11 performance cores
>>> - apple,mistral: A11 efficiency cores
>>>
>>> In the Apple A10, there are physical performance-efficiency cores that
>>> forms logical cores to software depending on the current p-state, and
>>> only one type of core may be active at one time.
>>>
>>> This follows the existing newest-first order.
>>>
>>> Signed-off-by: Nick Chan <towinchenmi@...il.com>
>>> ---
>>>  Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
>>>  1 file changed, 6 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
>>> index f308ff6c3532..3959e022079f 100644
>>> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
>>> @@ -89,6 +89,12 @@ properties:
>>>        - apple,blizzard
>>>        - apple,icestorm
>>>        - apple,firestorm
>>> +      - apple,mistral
>>> +      - apple,monsoon
>>> +      - apple,hurricane-zephyr
>>> +      - apple,twister
>>> +      - apple,typhoon
>>> +      - apple,cyclone
>>
>> Please keep alphabetical order. And no, just because earlier Hector
>> added stuff in reversed order, is not a reason to keep doing the same.
> Ack. All bindings added in this series except
> 
> Documentation/devicetree/bindings/arm/apple.yaml
> 
> will be changed to alphabetical order in v2.

Wait, that's not exactly what I meant. In Apple-specific bindings maybe
some chronological order was chosen earlier. If there is some known
order, you can keep it. But for common bindings (so like one here)we
prefer alphabetical.

Best regards,
Krzysztof


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ