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Message-ID: <e6991910-5058-4ef0-bfdf-6d33953535dd@kernel.org>
Date: Tue, 17 Sep 2024 15:47:09 +0200
From: Konrad Dybcio <konradybcio@...nel.org>
To: Rob Clark <robdclark@...il.com>, dri-devel@...ts.freedesktop.org
Cc: linux-arm-msm@...r.kernel.org, freedreno@...ts.freedesktop.org,
 Akhil P Oommen <quic_akhilpo@...cinc.com>,
 Connor Abbott <cwabbott0@...il.com>, Rob Clark <robdclark@...omium.org>,
 Sean Paul <sean@...rly.run>, Konrad Dybcio <konradybcio@...nel.org>,
 Abhinav Kumar <quic_abhinavk@...cinc.com>,
 Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
 Marijn Suijten <marijn.suijten@...ainline.org>,
 David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
 open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm/msm/a6xx+: Insert a fence wait before SMMU table
 update

On 13.09.2024 9:51 PM, Rob Clark wrote:
> From: Rob Clark <robdclark@...omium.org>
> 
> The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
> devices (x1-85, possibly others), it seems to pass that barrier while
> there are still things in the event completion FIFO waiting to be
> written back to memory.

Can we try to force-fault around here on other GPUs and perhaps
limit this workaround?

Akhil, do we have any insight on this?

Konrad

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