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Message-ID: <20240917145203.2nznqdkrsfanttex@hu-akhilpo-hyd.qualcomm.com>
Date: Tue, 17 Sep 2024 20:22:03 +0530
From: Akhil P Oommen <quic_akhilpo@...cinc.com>
To: Konrad Dybcio <konradybcio@...nel.org>
CC: Rob Clark <robdclark@...il.com>, <dri-devel@...ts.freedesktop.org>,
<linux-arm-msm@...r.kernel.org>, <freedreno@...ts.freedesktop.org>,
"Connor
Abbott" <cwabbott0@...il.com>,
Rob Clark <robdclark@...omium.org>, Sean Paul
<sean@...rly.run>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
"Dmitry
Baryshkov" <dmitry.baryshkov@...aro.org>,
Marijn Suijten
<marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, "Daniel
Vetter" <daniel@...ll.ch>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm/msm/a6xx+: Insert a fence wait before SMMU table
update
On Tue, Sep 17, 2024 at 03:47:09PM +0200, Konrad Dybcio wrote:
> On 13.09.2024 9:51 PM, Rob Clark wrote:
> > From: Rob Clark <robdclark@...omium.org>
> >
> > The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
> > devices (x1-85, possibly others), it seems to pass that barrier while
> > there are still things in the event completion FIFO waiting to be
> > written back to memory.
>
> Can we try to force-fault around here on other GPUs and perhaps
> limit this workaround?
>
> Akhil, do we have any insight on this?
Nothing at the moment. I will check this further.
-Akhil.
>
> Konrad
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