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Message-ID: <cd40d57c-51d2-480e-80ef-7d87dd96a6b2@kernel.org>
Date: Fri, 20 Sep 2024 13:22:35 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Konrad Dybcio <konradybcio@...nel.org>, Qiang Yu <quic_qianyu@...cinc.com>
Cc: manivannan.sadhasivam@...aro.org, vkoul@...nel.org, kishon@...nel.org,
 robh@...nel.org, andersson@...nel.org, krzk+dt@...nel.org,
 conor+dt@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
 abel.vesa@...aro.org, quic_msarkar@...cinc.com, quic_devipriy@...cinc.com,
 dmitry.baryshkov@...aro.org, kw@...ux.com, lpieralisi@...nel.org,
 neil.armstrong@...aro.org, linux-arm-msm@...r.kernel.org,
 linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
 linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
 linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy:
 Document the X1E80100 QMP PCIe PHY Gen4 x8

On 19/09/2024 17:37, Konrad Dybcio wrote:
> On 19.09.2024 4:03 PM, Qiang Yu wrote:
>>
>> On 9/16/2024 11:15 PM, Krzysztof Kozlowski wrote:
>>> On Fri, Sep 13, 2024 at 01:37:20AM -0700, Qiang Yu wrote:
>>>> PCIe 3rd instance of X1E80100 support Gen 4x8 which needs different 8 lane
>>>> capable QMP PCIe PHY. Document Gen 4x8 PHY as separate module.
>>> And this is really different hardware? Not just different number of lanes? We discussed it, but I don't see the explanation in commit msg.
>> Yes, PCIe3 use a different phy that supports 8 lanes and provides
>> additional register set, txz and rxz. It is not a bifurcation mode which
>> actually combines two same phys like PCIe6a. It's also not just different
>> number of lanes. Will explain this in commit msg.
> 
> Krzysztof, this PHY is new and has a different hardware revision (v6.30 as
> opposed to v6.20? of the other ones)

It's fine for me then, but I expect commit msg to say this. For I am a
bear of very little brain, and I forget the topic right after I close
the email.

Best regards,
Krzysztof


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