linux-kernel - Re: [PATCH v3 2/2] PCI: mediatek-gen3: Add support for restricting link width

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Message-ID: <CAC=S1niSEG_9kFDBGL+i=MjqvfiuQBmAhv+7He9A3_7PXUi8Gg@mail.gmail.com>
Date: Mon, 23 Sep 2024 18:08:14 +0800
From: Fei Shao <fshao@...omium.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: linux-pci@...r.kernel.org, ryder.lee@...iatek.com, 
	jianjun.wang@...iatek.com, lpieralisi@...nel.org, kw@...ux.com, 
	robh@...nel.org, bhelgaas@...gle.com, matthias.bgg@...il.com, 
	linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, kernel@...labora.com
Subject: Re: [PATCH v3 2/2] PCI: mediatek-gen3: Add support for restricting
 link width

On Wed, Sep 18, 2024 at 4:13 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com> wrote:
>
> Add support for restricting the port's link width by specifying
> the num-lanes devicetree property in the PCIe node.
>
> The setting is done in the GEN_SETTINGS register (in the driver
> named as PCIE_SETTING_REG), where each set bit in [11:8] activates
> a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2).
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>

Reviewed-by: Fei Shao <fshao@...omium.org>