linux-kernel - [PATCH v2 1/2] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode

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Message-Id: <20240924094430.272074-2-Delphine_CC_Chiu@wiwynn.com>
Date: Tue, 24 Sep 2024 17:44:29 +0800
From: Delphine CC Chiu <Delphine_CC_Chiu@...ynn.com>
To: patrick@...cx.xyz,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Joel Stanley <joel@....id.au>,
	Andrew Jeffery <andrew@...econstruct.com.au>
Cc: Ricky CX Wu <ricky.cx.wu.wiwynn@...il.com>,
	Delphine CC Chiu <Delphine_CC_Chiu@...ynn.com>,
	devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-aspeed@...ts.ozlabs.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH v2 1/2] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode

From: Ricky CX Wu <ricky.cx.wu.wiwynn@...il.com>

Revise quad mode to dual mode to keep the write protect feature for the
SPI flash because the WP pin is the same pin with IO2 pin in quad mode.

Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@...il.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@...ynn.com>
---
 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 98477792aa00..c4af50ba6999 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -105,7 +105,8 @@ flash@0 {
 		status = "okay";
 		m25p,fast-read;
 		label = "bmc";
-		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
 		spi-max-frequency = <50000000>;
 #include "openbmc-flash-layout-64.dtsi"
 	};
@@ -113,7 +114,8 @@ flash@1 {
 		status = "okay";
 		m25p,fast-read;
 		label = "bmc2";
-		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
 		spi-max-frequency = <50000000>;
 	};
 };
-- 
2.25.1