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Message-ID: <ZvLnx4LsFxf8+9mO@lizhi-Precision-Tower-5810>
Date: Tue, 24 Sep 2024 12:24:39 -0400
From: Frank Li <Frank.li@....com>
To: Richard Zhu <hongxing.zhu@....com>
Cc: l.stach@...gutronix.de, kwilczynski@...nel.org, bhelgaas@...gle.com,
lpieralisi@...nel.org, robh+dt@...nel.org, conor+dt@...nel.org,
shawnguo@...nel.org, krzysztof.kozlowski+dt@...aro.org,
festevam@...il.com, s.hauer@...gutronix.de,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
kernel@...gutronix.de, imx@...ts.linux.dev
Subject: Re: [PATCH v1 6/9] PCI: imx6: Make *_enable_ref_clk() function
symmetric
On Tue, Sep 24, 2024 at 11:27:41AM +0800, Richard Zhu wrote:
> Ensure the *_enable_ref_clk() function is symmetric by addressing missing
> disable parts on some platforms. Also, remove the duplicate
> imx7d_pcie_init_phy() function as it is the same as
> imx7d_pcie_enable_ref_clk().
>
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
Reviewed-by: Frank Li <Frank.Li@....com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 33 +++++++++++----------------
> 1 file changed, 13 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index f306f2e9dcce..5ec43d9f9784 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -388,13 +388,6 @@ static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie)
> return 0;
> }
>
> -static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie)
> -{
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
> -
> - return 0;
> -}
> -
> static int imx_pcie_init_phy(struct imx_pcie *imx_pcie)
> {
> regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> @@ -593,13 +586,13 @@ static int imx_pcie_attach_pd(struct device *dev)
>
> static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> {
> - if (enable)
> - regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
> -
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
> + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
> return 0;
> }
>
> +
> static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> {
> if (enable) {
> @@ -625,19 +618,20 @@ static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> {
> int offset = imx_pcie_grp_offset(imx_pcie);
>
> - if (enable) {
> - regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
> - regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
> - }
> -
> + regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
> + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
> + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
> + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
> + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
> return 0;
> }
>
> static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> {
> - if (!enable)
> - regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
> + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
> + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
> return 0;
> }
>
> @@ -1522,7 +1516,6 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .clks_cnt = ARRAY_SIZE(imx6q_clks),
> .mode_off[0] = IOMUXC_GPR12,
> .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> - .init_phy = imx7d_pcie_init_phy,
> .enable_ref_clk = imx7d_pcie_enable_ref_clk,
> .core_reset = imx7d_pcie_core_reset,
> },
> --
> 2.37.1
>
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