[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ZvLomXcbbiZ+LTP0@lizhi-Precision-Tower-5810>
Date: Tue, 24 Sep 2024 12:28:09 -0400
From: Frank Li <Frank.li@....com>
To: Richard Zhu <hongxing.zhu@....com>
Cc: l.stach@...gutronix.de, kwilczynski@...nel.org, bhelgaas@...gle.com,
lpieralisi@...nel.org, robh+dt@...nel.org, conor+dt@...nel.org,
shawnguo@...nel.org, krzysztof.kozlowski+dt@...aro.org,
festevam@...il.com, s.hauer@...gutronix.de,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
kernel@...gutronix.de, imx@...ts.linux.dev
Subject: Re: [PATCH v1 9/9] arm64: dts: imx95: Add ref clock for i.MX95 PCIe
On Tue, Sep 24, 2024 at 11:27:44AM +0800, Richard Zhu wrote:
> Add ref clock for i.MX95 PCIe.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
below nit.
Reviewed-by: Frank Li <Frank.Li@....com>
> ---
> arch/arm64/boot/dts/freescale/imx95.dtsi | 25 ++++++++++++++++++++----
> 1 file changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 1bbf9a0468f6..e66be264c2f2 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -221,6 +221,13 @@ core5 {
> };
> };
>
> + clk_dummy: clock-dummy {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + clock-output-names = "clk_dummy";
> + };
> +
> clk_ext1: clock-ext1 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -1055,6 +1062,14 @@ smmu: iommu@...d0000 {
> };
> };
>
> + hsio_blk_ctl: syscon@...100c0 {
> + compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
> + reg = <0x0 0x4c0100c0 0x0 0x4>;
> + #clock-cells = <1>;
> + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> + clocks = <&clk_dummy>;
nit: move clocks above power-domains
> + };
> +
> pcie0: pcie@...00000 {
> compatible = "fsl,imx95-pcie";
> reg = <0 0x4c300000 0 0x10000>,
> @@ -1082,8 +1097,9 @@ pcie0: pcie@...00000 {
> clocks = <&scmi_clk IMX95_CLK_HSIO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> + <&hsio_blk_ctl 0>;
> + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
> assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> @@ -1149,8 +1165,9 @@ pcie1: pcie@...80000 {
> clocks = <&scmi_clk IMX95_CLK_HSIO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> + <&hsio_blk_ctl 0>;
> + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
> assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> --
> 2.37.1
>
Powered by blists - more mailing lists