linux-kernel - Re: [PATCH 4/4] soc: marvell: rvu-pf: Handle function level reset (FLR) IRQs for VFs

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Message-ID:
 <DM6PR18MB32895C157AEEE0D3C1995A8EB8692@DM6PR18MB3289.namprd18.prod.outlook.com>
Date: Wed, 25 Sep 2024 12:46:51 +0000
From: Anshumali Gaur <agaur@...vell.com>
To: Alexander Sverdlin <alexander.sverdlin@...il.com>,
        "conor.dooley@...rochip.com" <conor.dooley@...rochip.com>,
        "ulf.hansson@...aro.org" <ulf.hansson@...aro.org>,
        "arnd@...db.de"
	<arnd@...db.de>,
        "linus.walleij@...aro.org" <linus.walleij@...aro.org>,
        "nikita.shubin@...uefel.me" <nikita.shubin@...uefel.me>,
        "vkoul@...nel.org"
	<vkoul@...nel.org>,
        "cyy@...self.name" <cyy@...self.name>,
        "krzysztof.kozlowski@...aro.org" <krzysztof.kozlowski@...aro.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Sunil Kovvuri
 Goutham <sgoutham@...vell.com>
Subject: Re: [PATCH 4/4] soc: marvell: rvu-pf: Handle function level reset
 (FLR) IRQs for VFs



> -----Original Message-----
> From: Alexander Sverdlin <alexander.sverdlin@...il.com>
> Sent: Wednesday, September 25, 2024 2:49 PM
> To: Anshumali Gaur <agaur@...vell.com>; conor.dooley@...rochip.com;
> ulf.hansson@...aro.org; arnd@...db.de; linus.walleij@...aro.org;
> nikita.shubin@...uefel.me; vkoul@...nel.org; cyy@...self.name;
> krzysztof.kozlowski@...aro.org; linux-kernel@...r.kernel.org; Sunil Kovvuri
> Goutham <sgoutham@...vell.com>
> Subject: Re: [PATCH 4/4] soc: marvell: rvu-pf: Handle function level
> reset (FLR) IRQs for VFs
> 
> Hi Anshumali! On Wed, 2024-09-25 at 09: 13 +0000, Anshumali Gaur wrote: > > >
> +static irqreturn_t rvu_gen_pf_me_intr_handler(int irq, void *pf_irq) > > > +{ > > >
> + struct gen_pf_dev *pfdev = (struct gen_pf_dev *)pf_irq;
> Hi Anshumali!
> 
> On Wed, 2024-09-25 at 09:13 +0000, Anshumali Gaur wrote:
> > > > +static irqreturn_t rvu_gen_pf_me_intr_handler(int irq, void
> > > > +*pf_irq) {
> > > > +	struct gen_pf_dev *pfdev = (struct gen_pf_dev *)pf_irq;
> > > > +	int vf, reg, num_reg = 1;
> > > > +	u64 intr;
> > > > +
> > > > +	if (pfdev->total_vfs > 64)
> > > > +		num_reg = 2;
> > > > +
> > > > +	for (reg = 0; reg < num_reg; reg++) {
> > > > +		intr = readq(pfdev->reg_base + RVU_PF_VFME_INTX(reg));
> > > > +		if (!intr)
> > > > +			continue;
> > > > +		for (vf = 0; vf < 64; vf++) {
> > > > +			if (!(intr & BIT_ULL(vf)))
> > > > +				continue;
> > > > +			/* clear trpend bit */
> > > > +			writeq(BIT_ULL(vf), pfdev->reg_base +
> > > RVU_PF_VFTRPENDX(reg));
> > > > +			/* clear interrupt */
> > > > +			writeq(BIT_ULL(vf), pfdev->reg_base +
> > > RVU_PF_VFME_INTX(reg));
> > > > +		}
> > > > +	}
> > >
> > > Should anything else have been performed in the IRQ handler besides
> > > acknowledging the IRQ request?
> > >
> > We are just acknowledging the IRQ request here.
> 
> But what's the goal of requesting the IRQ in the first place then?
> 
In this PCIe Master enable intr handler we are clearing the PCI Transaction pending bits of PFVF devices
until it is cleared 
This API is called whenever the device gets reset.

Thanks and Regards,
Anshumali Gaur
> --
> Alexander Sverdlin.