| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20240925131547.42396-3-luxu.kernel@bytedance.com>
Date: Wed, 25 Sep 2024 21:15:47 +0800
From: Xu Lu <luxu.kernel@...edance.com>
To: paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu,
andy.chiu@...ive.com,
guoren@...nel.org,
christoph.muellner@...ll.eu,
ajones@...tanamicro.com
Cc: linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
lihangjing@...edance.com,
dengliang.1214@...edance.com,
xieyongji@...edance.com,
chaiwen.cc@...edance.com,
Xu Lu <luxu.kernel@...edance.com>
Subject: [PATCH v3 2/2] riscv: Use Zawrs to accelerate IPI to idle cpu
When sending IPI to a cpu which has entered idle state using Zawrs
extension, there is no need to send a physical software interrupt.
Instead, we can write the IPI information to the address reserved by
target cpu, which will wake it from WRS.NTO. Then the target cpu can
handle the IPI directly without falling into traditional interrupt
handling routine.
Signed-off-by: Xu Lu <luxu.kernel@...edance.com>
---
arch/riscv/include/asm/processor.h | 14 +++++++
arch/riscv/include/asm/smp.h | 14 +++++++
arch/riscv/kernel/process.c | 65 +++++++++++++++++++++++++++++-
arch/riscv/kernel/smp.c | 51 ++++++++++++++++++-----
4 files changed, 131 insertions(+), 13 deletions(-)
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index d0dcdb7e7392..0dbc9390c3b2 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -164,6 +164,20 @@ static inline void wrs_nto(unsigned long *addr)
: : "memory");
}
+static inline void wrs_nto_if(int *addr, int val)
+{
+ int prev;
+
+ __asm__ __volatile__(
+ "lr.w %[p], %[a]\n\t"
+ "bne %[p], %[v], 1f\n\t"
+ ZAWRS_WRS_NTO "\n\t"
+ "1:\n\t"
+ : [p] "=&r" (prev), [a] "+A" (*addr)
+ : [v] "r" (val)
+ : "memory");
+}
+
extern phys_addr_t dma32_phys_limit;
struct device_node;
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 7ac80e9f2288..8f2dfbf20e89 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -19,6 +19,20 @@ extern unsigned long boot_cpu_hartid;
#include <linux/jump_label.h>
+enum ipi_message_type {
+ IPI_RESCHEDULE,
+ IPI_CALL_FUNC,
+ IPI_CPU_STOP,
+ IPI_CPU_CRASH_STOP,
+ IPI_IRQ_WORK,
+ IPI_TIMER,
+ IPI_MAX
+};
+
+int ipi_virq_base_get(void);
+
+irqreturn_t handle_IPI(int irq, void *data);
+
/*
* Mapping between linux logical cpu index and hartid.
*/
diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index 77769965609e..975b3f28e8c8 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -16,6 +16,7 @@
#include <linux/ptrace.h>
#include <linux/uaccess.h>
#include <linux/static_call.h>
+#include <linux/hardirq.h>
#include <asm/unistd.h>
#include <asm/processor.h>
@@ -27,6 +28,7 @@
#include <asm/cpuidle.h>
#include <asm/vector.h>
#include <asm/cpufeature.h>
+#include <asm/smp.h>
#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
#include <linux/stackprotector.h>
@@ -36,6 +38,8 @@ EXPORT_SYMBOL(__stack_chk_guard);
extern asmlinkage void ret_from_fork(void);
+DEFINE_PER_CPU(atomic_t, idle_ipi_mask);
+
static __cpuidle void default_idle(void)
{
/*
@@ -47,6 +51,16 @@ static __cpuidle void default_idle(void)
wait_for_interrupt();
}
+static __cpuidle void default_idle_enter(void)
+{
+ /* Do nothing */
+}
+
+static __cpuidle void default_idle_exit(void)
+{
+ /* Do nothing */
+}
+
static __cpuidle void wrs_idle(void)
{
/*
@@ -55,10 +69,42 @@ static __cpuidle void wrs_idle(void)
* to entering WRS.NTO.
*/
mb();
+#ifdef CONFIG_SMP
+ wrs_nto_if(&this_cpu_ptr(&idle_ipi_mask)->counter, BIT(IPI_MAX));
+#else
wrs_nto(¤t_thread_info()->flags);
+#endif
+}
+
+static __cpuidle void wrs_idle_enter(void)
+{
+#ifdef CONFIG_SMP
+ atomic_set(this_cpu_ptr(&idle_ipi_mask), BIT(IPI_MAX));
+#endif
+}
+
+static __cpuidle void wrs_idle_exit(void)
+{
+#ifdef CONFIG_SMP
+ int pending;
+ unsigned long flags;
+ enum ipi_message_type ipi;
+
+ local_irq_save(flags);
+ pending = atomic_xchg_relaxed(this_cpu_ptr(&idle_ipi_mask), 0);
+ for (ipi = IPI_RESCHEDULE; ipi < IPI_MAX; ipi++)
+ if (pending & BIT(ipi)) {
+ irq_enter();
+ handle_IPI(ipi_virq_base_get() + ipi, NULL);
+ irq_exit();
+ }
+ local_irq_restore(flags);
+#endif
}
DEFINE_STATIC_CALL_NULL(riscv_idle, default_idle);
+DEFINE_STATIC_CALL_NULL(riscv_idle_enter, default_idle_enter);
+DEFINE_STATIC_CALL_NULL(riscv_idle_exit, default_idle_exit);
void __cpuidle cpu_do_idle(void)
{
@@ -70,13 +116,28 @@ void __cpuidle arch_cpu_idle(void)
cpu_do_idle();
}
+void __cpuidle arch_cpu_idle_enter(void)
+{
+ static_call(riscv_idle_enter)();
+}
+
+void __cpuidle arch_cpu_idle_exit(void)
+{
+ static_call(riscv_idle_exit)();
+}
+
void __init select_idle_routine(void)
{
if (IS_ENABLED(CONFIG_RISCV_ZAWRS_IDLE) &&
- riscv_has_extension_likely(RISCV_ISA_EXT_ZAWRS))
+ riscv_has_extension_likely(RISCV_ISA_EXT_ZAWRS)) {
static_call_update(riscv_idle, wrs_idle);
- else
+ static_call_update(riscv_idle_enter, wrs_idle_enter);
+ static_call_update(riscv_idle_exit, wrs_idle_exit);
+ } else {
static_call_update(riscv_idle, default_idle);
+ static_call_update(riscv_idle_enter, default_idle_enter);
+ static_call_update(riscv_idle_exit, default_idle_exit);
+ }
}
int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 8e6eb64459af..6e7d41ed4144 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -26,16 +26,6 @@
#include <asm/cacheflush.h>
#include <asm/cpu_ops.h>
-enum ipi_message_type {
- IPI_RESCHEDULE,
- IPI_CALL_FUNC,
- IPI_CPU_STOP,
- IPI_CPU_CRASH_STOP,
- IPI_IRQ_WORK,
- IPI_TIMER,
- IPI_MAX
-};
-
unsigned long __cpuid_to_hartid_map[NR_CPUS] __ro_after_init = {
[0 ... NR_CPUS-1] = INVALID_HARTID
};
@@ -94,13 +84,47 @@ static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
}
#endif
+#ifdef CONFIG_RISCV_ZAWRS_IDLE
+DECLARE_PER_CPU(atomic_t, idle_ipi_mask);
+#endif
+
static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
{
+#ifdef CONFIG_RISCV_ZAWRS_IDLE
+ int cpu, val;
+
+ asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop", 0, RISCV_ISA_EXT_ZAWRS, 1)
+ : : : : no_zawrs);
+
+ for_each_cpu(cpu, mask) {
+ val = atomic_fetch_or_relaxed(BIT(op), per_cpu_ptr(&idle_ipi_mask, cpu));
+ if (likely(!(val & BIT(IPI_MAX))))
+ __ipi_send_mask(ipi_desc[op], cpumask_of(cpu));
+ }
+
+ return;
+
+no_zawrs:
+#endif
__ipi_send_mask(ipi_desc[op], mask);
}
static void send_ipi_single(int cpu, enum ipi_message_type op)
{
+#ifdef CONFIG_RISCV_ZAWRS_IDLE
+ int val;
+
+ asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop", 0, RISCV_ISA_EXT_ZAWRS, 1)
+ : : : : no_zawrs);
+
+ val = atomic_fetch_or_relaxed(BIT(op), per_cpu_ptr(&idle_ipi_mask, cpu));
+ if (likely(!(val & BIT(IPI_MAX))))
+ __ipi_send_mask(ipi_desc[op], cpumask_of(cpu));
+
+ return;
+
+no_zawrs:
+#endif
__ipi_send_mask(ipi_desc[op], cpumask_of(cpu));
}
@@ -111,7 +135,7 @@ void arch_irq_work_raise(void)
}
#endif
-static irqreturn_t handle_IPI(int irq, void *data)
+irqreturn_t handle_IPI(int irq, void *data)
{
int ipi = irq - ipi_virq_base;
@@ -323,3 +347,8 @@ void arch_smp_send_reschedule(int cpu)
send_ipi_single(cpu, IPI_RESCHEDULE);
}
EXPORT_SYMBOL_GPL(arch_smp_send_reschedule);
+
+int ipi_virq_base_get(void)
+{
+ return ipi_virq_base;
+}
--
2.20.1
Powered by blists - more mailing lists