linux-kernel - Re: [PATCH v2] clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set

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Message-ID: <jlmnxzkferigmhh5akcr5uumrdychjxyy2flftx5u2sg2w62aa@566u2lqj5od2>
Date: Thu, 26 Sep 2024 00:28:40 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Barnabás Czémán <barnabas.czeman@...nlining.org>
Cc: Bjorn Andersson <andersson@...nel.org>, 
	Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Satya Priya Kakitapalli <quic_skakitap@...cinc.com>, Konrad Dybcio <konradybcio@...nel.org>, 
	Abhishek Sahu <absahu@...eaurora.org>, linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Stephen Boyd <sboyd@...eaurora.org>
Subject: Re: [PATCH v2] clk: qcom: clk-alpha-pll: Fix pll post div mask when
 width is not set

On Wed, Sep 25, 2024 at 08:33:20PM GMT, Barnabás Czémán wrote:
> Many qcom clock drivers do not have .width set. In that case value of
> (p)->width - 1 will be negative which breaks clock tree. Fix this
> by checking if width is zero, and pass 3 to GENMASK if that's the case.
> 
> Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
> Fixes: 2c4553e6c485 ("clk: qcom: clk-alpha-pll: Fix the pll post div mask")

I think one Fixes tag should be enough.

Nevertheless,

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>

> Signed-off-by: Barnabás Czémán <barnabas.czeman@...nlining.org>
> ---
> Changes in v2:
> - Pass 3 to GENMASK instead of 0.
> - Add more Fixes tag for reference root cause.
> - Link to v1: https://lore.kernel.org/r/20240925-fix-postdiv-mask-v1-1-f70ba55f415e@mainlining.org
> ---
>  drivers/clk/qcom/clk-alpha-pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

-- 
With best wishes
Dmitry