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Message-Id: <1727245477-15961-2-git-send-email-hongxing.zhu@nxp.com>
Date: Wed, 25 Sep 2024 14:24:29 +0800
From: Richard Zhu <hongxing.zhu@....com>
To: l.stach@...gutronix.de,
kwilczynski@...nel.org,
bhelgaas@...gle.com,
lpieralisi@...nel.org,
frank.li@....com,
robh+dt@...nel.org,
conor+dt@...nel.org,
shawnguo@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
festevam@...il.com,
s.hauer@...gutronix.de
Cc: linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
kernel@...gutronix.de,
imx@...ts.linux.dev,
Richard Zhu <hongxing.zhu@....com>
Subject: [PATCH v2 1/9] dt-bindings: imx6q-pcie: Add ref clock for i.MX95 PCIe
Previous reference clock of i.MX95 is on when system boot to kernel. But
boot firmware change the behavor, it is off when boot. So it needs be turn
on when it is used. Also it needs be turn off/on when suspend and resume.
Add one ref clock for i.MX95 PCIe. Increase clocks' maxItems to 5 and keep
the same restriction with other compatible string.
Signed-off-by: Richard Zhu <hongxing.zhu@....com>
---
.../bindings/pci/fsl,imx6q-pcie-common.yaml | 4 +--
.../bindings/pci/fsl,imx6q-pcie.yaml | 25 ++++++++++++++++---
2 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
index a8b34f58f8f4..cddbe21f99f2 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
@@ -17,11 +17,11 @@ description:
properties:
clocks:
minItems: 3
- maxItems: 4
+ maxItems: 5
clock-names:
minItems: 3
- maxItems: 4
+ maxItems: 5
num-lanes:
const: 1
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 1e05c560d797..4c76cd3f98a9 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -40,10 +40,11 @@ properties:
- description: PCIe PHY clock.
- description: Additional required clock entry for imx6sx-pcie,
imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
+ - description: PCIe reference clock.
clock-names:
minItems: 3
- maxItems: 4
+ maxItems: 5
interrupts:
items:
@@ -127,7 +128,7 @@ allOf:
then:
properties:
clocks:
- minItems: 4
+ maxItems: 4
clock-names:
items:
- const: pcie
@@ -140,11 +141,10 @@ allOf:
compatible:
enum:
- fsl,imx8mq-pcie
- - fsl,imx95-pcie
then:
properties:
clocks:
- minItems: 4
+ maxItems: 4
clock-names:
items:
- const: pcie
@@ -200,6 +200,23 @@ allOf:
- const: mstr
- const: slv
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx95-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - const: pcie_phy
+ - const: pcie_aux
+ - const: ref
+
unevaluatedProperties: false
examples:
--
2.37.1
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