linux-kernel - Re: [PATCH 3/6] dt-bindings: display: mediatek: Fix clocks count constraint for new SoCs

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Message-ID: <2821ef09-1b32-082d-69d1-e09a3a302447@mediatek.com>
Date: Wed, 25 Sep 2024 16:42:59 +0800
From: Macpaul Lin <macpaul.lin@...iatek.com>
To: Conor Dooley <conor@...nel.org>, AngeloGioacchino Del Regno
	<angelogioacchino.delregno@...labora.com>, <moudy.ho@...iatek.com>,
	<macross.chen@...iatek.com>
CC: Chun-Kuang Hu <chunkuang.hu@...nel.org>, Philipp Zabel
	<p.zabel@...gutronix.de>, Maarten Lankhorst
	<maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
	Thomas Zimmermann <tzimmermann@...e.de>, David Airlie <airlied@...il.com>,
	Simona Vetter <simona@...ll.ch>, Rob Herring <robh@...nel.org>, "Krzysztof
 Kozlowski" <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Yong Wu
	<yong.wu@...iatek.com>, Joerg Roedel <joro@...tes.org>, Will Deacon
	<will@...nel.org>, Robin Murphy <robin.murphy@....com>, Matthias Brugger
	<matthias.bgg@...il.com>, <dri-devel@...ts.freedesktop.org>,
	<linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <iommu@...ts.linux.dev>,
	<linux-arm-kernel@...ts.infradead.org>, Alexandre Mergnat
	<amergnat@...libre.com>, Bear Wang <bear.wang@...iatek.com>, Pablo Sun
	<pablo.sun@...iatek.com>, Macpaul Lin <macpaul@...il.com>, Sen Chu
	<sen.chu@...iatek.com>, Chris-qj chen <chris-qj.chen@...iatek.com>, "MediaTek
 Chromebook Upstream" <Project_Global_Chrome_Upstream_Group@...iatek.com>,
	Chen-Yu Tsai <wenst@...omium.org>
Subject: Re: [PATCH 3/6] dt-bindings: display: mediatek: Fix clocks count
 constraint for new SoCs


On 9/25/24 00:00, Conor Dooley wrote:
> On Tue, Sep 24, 2024 at 01:42:01PM +0200, AngeloGioacchino Del Regno wrote:
>> Il 24/09/24 12:31, Macpaul Lin ha scritto:
>>> The display node in mt8195.dtsi was triggering a CHECK_DTBS error due
>>> to an excessively long 'clocks' property:
>>>     display@...06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long
>>>
>>> To resolve this issue, add "maxItems: 3" to the 'clocks' property in
>>> the DT schema.
>>>
>>> Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
>>> Signed-off-by: Macpaul Lin <macpaul.lin@...iatek.com>
>>> ---
>>>    .../devicetree/bindings/display/mediatek/mediatek,split.yaml     | 1 +
>>>    1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>>> index e4affc854f3d..42d2d483cc29 100644
>>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>>> @@ -57,6 +57,7 @@ properties:
>>>      clocks:
>>>        items:
>>>          - description: SPLIT Clock
>>
>> That's at least confusing (granted that it works) - either add a description for
>> each clock and then set `minItems: 1` (preferred), or remove this "SPLIT Clock"
>> description and allow a maximum of 3 clocks.
>>
>> Removing the description can be done - IMO - because "SPLIT Clock" is, well,
>> saying that the SPLIT block gets a SPLIT clock ... stating the obvious, anyway.
> 
> Right, but what are the other two new clocks? Are they as obvious?
> There's no clock-names here to give any more information as to what the
> other clocks are supposed to be.
> 
> Kinda unrelated, but I think that "SPLIT Clock" probably isn't what the
> name of the clock in the IP block is anyway, sounds more like the name
> for it on the provider end..

Thanks for the suggestions. I think Moudy could help on the new fixes
for both DT schem and mt8195.dtsi. This patch could be separated from
origin patch set.

Thanks
Macpaul Lin