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Message-ID: <20240927222400.GE12322@pendragon.ideasonboard.com>
Date: Sat, 28 Sep 2024 01:24:00 +0300
From: Laurent Pinchart <laurent.pinchart@...asonboard.com>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Sakari Ailus <sakari.ailus@...ux.intel.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Hans Verkuil <hverkuil-cisco@...all.nl>,
linux-media@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 03/16] media: platform: rzg2l-cru: rzg2l-csi2: Mark
sink and source pad with MUST_CONNECT flag
Hi Prabhakar,
Thank you for the patch.
On Tue, Sep 10, 2024 at 06:53:44PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Mark the sink and source pad with the MEDIA_PAD_FL_MUST_CONNECT flag to
> ensure pipeline validation fails if it is not connected.
The MUST_CONNECT flag only affects sink pads. That's not documented
though, and it seems that most drivers using the flag sets it on both
sink and source pads. That's probably a good practice, and the fact that
the flag is only checked for sink pads is more of an implementation
detail. This patch is thus fine.
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>
However, I think you should then set the flag on the source pad of the
IP entity in patch 02/16. You can keep my Rb.
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> index c7fdee347ac8..2f4c87ede8bf 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> @@ -795,13 +795,15 @@ static int rzg2l_csi2_probe(struct platform_device *pdev)
> csi2->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
> csi2->subdev.entity.ops = &rzg2l_csi2_entity_ops;
>
> - csi2->pads[RZG2L_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
> + csi2->pads[RZG2L_CSI2_SINK].flags = MEDIA_PAD_FL_SINK |
> + MEDIA_PAD_FL_MUST_CONNECT;
> /*
> * TODO: RZ/G2L CSI2 supports 4 virtual channels, as virtual
> * channels should be implemented by streams API which is under
> * development lets hardcode to VC0 for now.
> */
> - csi2->pads[RZG2L_CSI2_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
> + csi2->pads[RZG2L_CSI2_SOURCE].flags = MEDIA_PAD_FL_SOURCE |
> + MEDIA_PAD_FL_MUST_CONNECT;
> ret = media_entity_pads_init(&csi2->subdev.entity, 2, csi2->pads);
> if (ret)
> goto error_pm;
--
Regards,
Laurent Pinchart
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