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Message-ID: <20240930-siesta-dandy-cb83076f68f2@spud>
Date: Mon, 30 Sep 2024 14:47:27 +0100
From: Conor Dooley <conor@...nel.org>
To: pierre-henry.moussay@...rochip.com
Cc: Linux4Microchip@...rochip.com,
	Conor Dooley <conor.dooley@...rochip.com>,
	Daire McNamara <daire.mcnamara@...rochip.com>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [linux][PATCH v2 07/20] dt-bindings: clock: mpfs-ccc: Add
 PIC64GX compatibility

On Mon, Sep 30, 2024 at 10:54:36AM +0100, pierre-henry.moussay@...rochip.com wrote:
> From: Pierre-Henry Moussay <pierre-henry.moussay@...rochip.com>
> 
> PIC64GX SoC Clock Conditioning Circuitry is compatibles
> with the Polarfire SoC
> 
> Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@...rochip.com>
> ---
>  .../devicetree/bindings/clock/microchip,mpfs-ccc.yaml       | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> index f1770360798f..9a6b50527c42 100644
> --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> @@ -17,7 +17,11 @@ description: |
>  
>  properties:
>    compatible:
> -    const: microchip,mpfs-ccc
> +    oneOf:
> +      - items:
> +          - const: microchip,pic64gx-ccc
> +          - const: microchip,mpfs-ccc
> +      - const: microchip,mpfs-ccc

Acked-by: Conor Dooley <conor.dooley@...rochip.com>

>  
>    reg:
>      items:
> -- 
> 2.30.2
> 
> 

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