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Message-Id: <20241001024356.1096072-26-anshuman.khandual@arm.com> Date: Tue, 1 Oct 2024 08:13:34 +0530 From: Anshuman Khandual <anshuman.khandual@....com> To: linux-kernel@...r.kernel.org, kvmarm@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org, maz@...nel.org Cc: Anshuman Khandual <anshuman.khandual@....com>, Oliver Upton <oliver.upton@...ux.dev>, James Morse <james.morse@....com>, Suzuki K Poulose <suzuki.poulose@....com>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>, Mark Brown <broonie@...nel.org> Subject: [PATCH 25/47] arm64/sysreg: Add register fields for SPMCR_EL0 This adds register fields for SPMCR_EL0 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas <catalin.marinas@....com> Cc: Will Deacon <will@...nel.org> Cc: Mark Brown <broonie@...nel.org> Cc: linux-arm-kernel@...ts.infradead.org Cc: linux-kernel@...r.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@....com> --- arch/arm64/tools/sysreg | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 300c213f39da..770c7ae23ce8 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -165,6 +165,19 @@ Sysreg PMCCNTSVR_EL1 2 0 14 11 7 Field 63:0 CCNT EndSysreg +Sysreg SPMCR_EL0 2 3 9 12 0 +Res0 63:12 +Field 11 TR0 +Field 10 HDBG +Field 9 FZ0 +Field 8 NA +Res0 7:5 +Field 4 EX +Res0 3:2 +Field 1 P +Field 0 E +EndSysreg + Sysreg SPMSCR_EL1 2 7 9 14 7 Field 63:32 IMP_DEF Field 31 RAO -- 2.25.1
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