linux-kernel - Re: [PATCH v2 3/6] nvmem: mtk-efuse: Enable postprocess for mt8188 GPU speed binning

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Message-ID: <908e6fcb-d1bc-4ab1-b4b8-6a13096b837c@collabora.com>
Date: Tue, 1 Oct 2024 17:18:16 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Pablo Sun <pablo.sun@...iatek.com>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
 linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 3/6] nvmem: mtk-efuse: Enable postprocess for mt8188
 GPU speed binning

Il 01/10/24 05:38, Pablo Sun ha scritto:
> Hi Angelo,
> 
> 
> On 9/30/24 17:40, AngeloGioacchino Del Regno wrote:
>> Il 27/09/24 12:30, Pablo Sun ha scritto:
>>> Similar to mt8186, the efuse data for mt8188's GPU speed binning
>>> requires post-process to convert the bit field format expected
>>> by the OPP table.
>>>
>>> Since mt8188 efuse is not compatible to mt8186, add a new compatible
>>> entry for mt8188 and enable postprocess.
>>>
>>> Signed-off-by: Pablo Sun <pablo.sun@...iatek.com>
>>
>> I know I told you to just reuse the pdata from 8186, but there's something else
>> that came to mind, here...
>>
>> ...actually, the efuse block from 8188 is indeed compatible with 8186, meaning
>> that the register r/w, etc, are all the same (bar the addresses, yes)
>>
>> So, I wonder if it's not just a better idea to not even add mt8188-efuse in this
>> driver's of_device_id array, and just add that to the binding so that we permit
>> using
>>          efuse: efuse@...20000 {
>>              compatible = "mediatek,mt8188-efuse",
>>                       "mediatek,mt8186-efuse", "mediatek,efuse";
>>              [etc]
>>          }
> 
> Thanks for proposing this. I agree that in the case of Mali GPU speed binning
> info, mt8188 behaves exactly the same as mt8186, only the cell addresses are
> different.
> 
> I wrote "mt8188 efuse is not compatible to mt8186" because I thought
> different eFuse cell layout leads to incompatibility, but it is correct that
> the cell layout differences can be expressed by the device tree nodes,
> so they are actually compatible in terms of hardware interface.
> 
> I'll drop this patch ("nvmem: mtk-efuse: Enable postprocess for mt8188 GPU speed 
> binning")
> in v3 and update dt-binding "mediatek,efuse.yaml" instead.
> 
>> Means that in mediatek,efuse.yaml you'll have to add...
>>
>>        - items:
>>            - enum:
>>                - mediatek,mt8188-efuse
>>            - const: mediatek,mt8186-efuse
>>            - const: mediatek,efuse <---- or without this, even.
>>
>> In the end, the "mediatek,efuse" property is somewhat deprecated, so that'd
>> also be a good time to start the dropping process, as I imagine that future SoCs
>> would also need the same speedbin transformations - which means that they'll all
>> be compatible with 8186....
> [snip]
> 
> But I am not sure if we should now drop "mediatek,efuse". The post-process for
> GPU speed binning info is only applicable to ARM Mali. Since there are MediaTek
> SoCs that are not using ARM Mali, or not having GPU at all, would it make more sense
> to keep the "mediatek,efuse" fallback compatible for those cases?
> 
> 

No, not really... because a specific SoC may *either* have Mali *or* PowerVR...

Counting that every SoC will, in any case, need a model-specific compatible (as in,
you can't ever have `compatible = "mediatek,efuse"`, but you will always have
`compatible = "mediatek,mt(model)", "mediatek,mt(othermodel)"` or similar), you
will still have to add that new SoC to the binding.

In case, that SoC can be still added to the list in the driver if there's any
incompatibility with the others (such as different register layout or binning
interpreter).

But then, keep in mind that the code that interprets the binning data in the fuses
is converting it from MediaTek format (1-2-3-4..etc) to the "generic" format that
is required by the OPP framework, which is *not* specific to ARM Mali.

Just to say - if the (MediaTek) format of the fuse data for binning is the same
for both PVR and Mali (so, it's still always 1,2,3,4,etc), then there wouldn't be
any incompatibility between the two, as PVR anyway uses OPP tables as much as Mali.

Cheers,
Angelo