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Message-Id: <20241001161042.465584-7-chang.seok.bae@intel.com>
Date: Tue, 1 Oct 2024 09:10:41 -0700
From: "Chang S. Bae" <chang.seok.bae@...el.com>
To: linux-kernel@...r.kernel.org
Cc: x86@...nel.org,
tglx@...utronix.de,
mingo@...hat.com,
bp@...en8.de,
dave.hansen@...ux.intel.com,
chang.seok.bae@...el.com
Subject: [PATCH RFC 6/7] x86/microcode/intel_staging: Support mailbox data transfer
The staging architecture features a narrowed interface for data transfer.
Instead of allocating MMIO space based on data chunk size, it utilizes
two data registers: one for reading and one for writing, enforcing the
serialization of read and write operations. Additionally, it defines a
mailbox data format.
To facilitate data transfer, implement helper functions in line with this
specified format for reading and writing staging data. This mailbox
format is a customized version and is not compatible with the existing
mailbox code, so reuse is not feasible.
Signed-off-by: Chang S. Bae <chang.seok.bae@...el.com>
---
arch/x86/kernel/cpu/microcode/intel_staging.c | 55 ++++++++++++++++++-
1 file changed, 52 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/microcode/intel_staging.c b/arch/x86/kernel/cpu/microcode/intel_staging.c
index 9989a78f9ef2..d56bad30164c 100644
--- a/arch/x86/kernel/cpu/microcode/intel_staging.c
+++ b/arch/x86/kernel/cpu/microcode/intel_staging.c
@@ -3,6 +3,7 @@
#define pr_fmt(fmt) "microcode: " fmt
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/pci_ids.h>
#include "internal.h"
@@ -11,17 +12,44 @@
#define MBOX_CONTROL_OFFSET 0x0
#define MBOX_STATUS_OFFSET 0x4
+#define MBOX_WRDATA_OFFSET 0x8
+#define MBOX_RDDATA_OFFSET 0xc
#define MASK_MBOX_CTRL_ABORT BIT(0)
+#define MASK_MBOX_CTRL_GO BIT(31)
#define MASK_MBOX_STATUS_ERROR BIT(2)
#define MASK_MBOX_STATUS_READY BIT(31)
+#define MASK_MBOX_RESP_SUCCESS BIT(0)
+#define MASK_MBOX_RESP_PROGRESS BIT(1)
+#define MASK_MBOX_RESP_ERROR BIT(2)
+
+#define MBOX_CMD_LOAD 0x3
+#define MBOX_OBJ_STAGING 0xb
+#define MBOX_HDR (PCI_VENDOR_ID_INTEL | (MBOX_OBJ_STAGING << 16))
+#define MBOX_HDR_SIZE 16
+
#define MBOX_XACTION_LEN PAGE_SIZE
#define MBOX_XACTION_MAX(imgsz) ((imgsz) * 2)
#define MBOX_XACTION_TIMEOUT (10 * MSEC_PER_SEC)
#define STAGING_OFFSET_END 0xffffffff
+#define DWORD_SIZE(s) ((s) / sizeof(u32))
+
+static inline u32 read_mbox_dword(void __iomem *base)
+{
+ u32 dword = readl(base + MBOX_RDDATA_OFFSET);
+
+ /* Inform the read completion to the staging firmware */
+ writel(0, base + MBOX_RDDATA_OFFSET);
+ return dword;
+}
+
+static inline void write_mbox_dword(void __iomem *base, u32 dword)
+{
+ writel(dword, base + MBOX_WRDATA_OFFSET);
+}
static inline void abort_xaction(void __iomem *base)
{
@@ -30,7 +58,18 @@ static inline void abort_xaction(void __iomem *base)
static void request_xaction(void __iomem *base, u32 *chunk, unsigned int chunksize)
{
- pr_debug_once("Need to implement staging mailbox loading code.\n");
+ unsigned int i, dwsize = DWORD_SIZE(chunksize);
+
+ write_mbox_dword(base, MBOX_HDR);
+ write_mbox_dword(base, dwsize + DWORD_SIZE(MBOX_HDR_SIZE));
+
+ write_mbox_dword(base, MBOX_CMD_LOAD);
+ write_mbox_dword(base, 0);
+
+ for (i = 0; i < dwsize; i++)
+ write_mbox_dword(base, chunk[i]);
+
+ writel(MASK_MBOX_CTRL_GO, base + MBOX_CONTROL_OFFSET);
}
static enum ucode_state wait_for_xaction(void __iomem *base)
@@ -55,8 +94,18 @@ static enum ucode_state wait_for_xaction(void __iomem *base)
static enum ucode_state read_xaction_response(void __iomem *base, unsigned int *offset)
{
- pr_debug_once("Need to implement staging response handler.\n");
- return UCODE_ERROR;
+ u32 flag;
+
+ WARN_ON_ONCE(read_mbox_dword(base) != MBOX_HDR);
+ WARN_ON_ONCE(read_mbox_dword(base) != DWORD_SIZE(MBOX_HDR_SIZE));
+
+ *offset = read_mbox_dword(base);
+
+ flag = read_mbox_dword(base);
+ if (flag & MASK_MBOX_RESP_ERROR)
+ return UCODE_ERROR;
+
+ return UCODE_OK;
}
static inline unsigned int get_chunksize(unsigned int totalsize, unsigned int offset)
--
2.43.0
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