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Message-ID: <cae8c6ca-d999-4b93-a82d-7a1f9924fcee@arm.com>
Date: Thu, 3 Oct 2024 09:46:08 +0530
From: Anshuman Khandual <anshuman.khandual@....com>
To: Oliver Upton <oliver.upton@...ux.dev>
Cc: linux-kernel@...r.kernel.org, kvmarm@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org, maz@...nel.org,
James Morse <james.morse@....com>, Suzuki K Poulose
<suzuki.poulose@....com>, Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, Mark Brown <broonie@...nel.org>
Subject: Re: [PATCH 47/47] KVM: arm64: nv: Add trap forwarding for FEAT_FGT2
described registers
On 10/1/24 20:16, Oliver Upton wrote:
> Hi Anshuman,
>
> On Tue, Oct 01, 2024 at 08:13:56AM +0530, Anshuman Khandual wrote:
>> +#define check_cntr_accessible(num) \
>> +static enum trap_behaviour check_cntr_accessible_##num(struct kvm_vcpu *vcpu) \
>> +{ \
>> + u64 mdcr_el2 = __vcpu_sys_reg(vcpu, MDCR_EL2); \
>> + int cntr = FIELD_GET(MDCR_EL2_HPMN_MASK, mdcr_el2); \
>> + \
>> + if (num >= cntr) \
>> + return BEHAVE_FORWARD_ANY; \
>> + return BEHAVE_HANDLE_LOCALLY; \
>> +} \
>> +
>> +check_cntr_accessible(0)
>> +check_cntr_accessible(1)
>> +check_cntr_accessible(2)
>> +check_cntr_accessible(3)
>> +check_cntr_accessible(4)
>> +check_cntr_accessible(5)
>> +check_cntr_accessible(6)
>> +check_cntr_accessible(7)
>> +check_cntr_accessible(8)
>> +check_cntr_accessible(9)
>> +check_cntr_accessible(10)
>> +check_cntr_accessible(11)
>> +check_cntr_accessible(12)
>> +check_cntr_accessible(13)
>> +check_cntr_accessible(14)
>> +check_cntr_accessible(15)
>> +check_cntr_accessible(16)
>> +check_cntr_accessible(17)
>> +check_cntr_accessible(18)
>> +check_cntr_accessible(19)
>> +check_cntr_accessible(20)
>> +check_cntr_accessible(21)
>> +check_cntr_accessible(22)
>> +check_cntr_accessible(23)
>> +check_cntr_accessible(24)
>> +check_cntr_accessible(25)
>> +check_cntr_accessible(26)
>> +check_cntr_accessible(27)
>> +check_cntr_accessible(28)
>> +check_cntr_accessible(29)
>> +check_cntr_accessible(30)
>
> I'd rather we not use templates for this problem. It bloats the kernel text
> as well as the trap encoding space.
Alright, fair point.
>
> I have a patch in the nested PMU series that uses a single complex trap
> ID to evaluate HPMN, and derives the index from ESR_EL2. I think it
> could also be extended to the PMEVCNTSVR<n> range as well.
Just for reference - the mentioned complex trap ID function from the
given link below.
static enum trap_behaviour check_mdcr_hpmn(struct kvm_vcpu *vcpu)
{
u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
u64 mask = kvm_pmu_accessible_counter_mask(vcpu);
unsigned int idx;
switch (sysreg) {
case SYS_PMEVTYPERn_EL0(0) ... SYS_PMEVTYPERn_EL0(30):
case SYS_PMEVCNTRn_EL0(0) ... SYS_PMEVCNTRn_EL0(30):
---------------------------------------------------------------------
Just add the new system register range here ?
+ case SYS_PMEVCNTSVR_EL1(0)... SYS_PMEVCNTSVR_EL1(31):
---------------------------------------------------------------------
idx = (sys_reg_CRm(sysreg) & 0x3) << 3 | sys_reg_Op2(sysreg);
break;
case SYS_PMXEVTYPER_EL0:
case SYS_PMXEVCNTR_EL0:
idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
break;
default:
/* Someone used this trap helper for something else... */
KVM_BUG_ON(1, vcpu->kvm);
return BEHAVE_HANDLE_LOCALLY;
}
/*
* Programming HPMN=0 is CONSTRAINED UNPREDICTABLE if FEAT_HPMN0 isn't
* implemented. Since KVM's ability to emulate HPMN=0 does not directly
* depend on hardware (all PMU registers are trapped), make the
* implementation choice that all counters are included in the second
* range reserved for EL2/EL3.
*/
return !(BIT(idx) & mask) ? (BEHAVE_FORWARD_RW | BEHAVE_IN_HOST_EL0) :
BEHAVE_HANDLE_LOCALLY;
}
>
> Also, keep in mind that the HPMN trap is annoying since it affects Host
> EL0 in addition to 'guest' ELs.
Does this require any more special handling other than the above complex trap
ID function ?
>
> [*]: https://lore.kernel.org/kvmarm/20240827002235.1753237-9-oliver.upton@linux.dev/
>
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