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Message-Id: <172802837479.20734.613907045651385407.b4-ty@linaro.org>
Date: Fri, 4 Oct 2024 10:55:19 +0300
From: Tudor Ambarus <tudor.ambarus@...aro.org>
To: linux-mtd@...ts.infradead.org,
linux-spi@...r.kernel.org,
linux-kernel@...r.kernel.org,
pratyush@...nel.org,
mwalle@...nel.org,
miquel.raynal@...tlin.com,
richard@....at,
vigneshr@...com,
broonie@...nel.org,
AlvinZhou <alvinzhou.tw@...il.com>
Cc: Tudor Ambarus <tudor.ambarus@...aro.org>,
chengminglin@...c.com.tw,
leoyu@...c.com.tw,
AlvinZhou <alvinzhou@...c.com.tw>
Subject: Re: [PATCH v10 0/6] Add octal DTR support for Macronix flash
On Thu, 26 Sep 2024 22:19:50 +0800, AlvinZhou wrote:
> Add method for Macronix Octal DTR Enable/Disable.
> Merge Tudor's patch "Allow specifying the byte order in DTR mode"
>
> v10:
> * Further explanation on adding Macronix manufacturer ID in ID table.
> * Correct some typos.
>
> [...]
Made the changes that I specified in replies. SFDP
"Command Sequences to Change to Octal DDR (8D-8D-8D) Mode" can be parsed
later on.
Applied to git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git,
spi-nor/next branch. Thanks!
[1/6] mtd: spi-nor: add Octal DTR support for Macronix flash
https://git.kernel.org/mtd/c/ccac858d2bdb
[2/6] spi: spi-mem: Allow specifying the byte order in Octal DTR mode
https://git.kernel.org/mtd/c/030ace430afc
[3/6] mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode
https://git.kernel.org/mtd/c/6a42bc97ccda
[4/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT
https://git.kernel.org/mtd/c/46b6256a68b4
[5/6] spi: mxic: Add support for swapping byte
https://git.kernel.org/mtd/c/50cb86f21ec2
[6/6] mtd: spi-nor: add support for Macronix Octal flash
https://git.kernel.org/mtd/c/afe1ea1344bb
Cheers,
--
Tudor Ambarus <tudor.ambarus@...aro.org>
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