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Message-ID: <20241005064307.18972-3-quic_rdwivedi@quicinc.com>
Date: Sat, 5 Oct 2024 12:13:06 +0530
From: Ram Kumar Dwivedi <quic_rdwivedi@...cinc.com>
To: <manivannan.sadhasivam@...aro.org>, <alim.akhtar@...sung.com>,
<avri.altman@....com>, <bvanassche@....org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <James.Bottomley@...senPartnership.com>,
<martin.petersen@...cle.com>, <agross@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-scsi@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_narepall@...cinc.com>, <quic_nitirawa@...cinc.com>,
<quic_rdwivedi@...cinc.com>
Subject: [PATCH V1 2/3] arm64: dts: qcom: sm8650: Add ICE algorithm entries
There are three algorithms supported for inline crypto engine:
Floor based, Static and Instantaneous algorithm.
Add ice algorithm entries and enable instantaneous algorithm
by default.
Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@...cinc.com>
Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@...cinc.com>
Co-developed-by: Nitin Rawat <quic_nitirawa@...cinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@...cinc.com>
Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@...cinc.com>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 9d9bbb9aca64..56a7ca6a3af4 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2590,6 +2590,25 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
#reset-cells = <1>;
status = "disabled";
+
+ ice_cfg: ice-config {
+ alg1 {
+ alg-name = "alg1";
+ rx-alloc-percent = <60>;
+ status = "disabled";
+ };
+
+ alg2 {
+ alg-name = "alg2";
+ status = "disabled";
+ };
+
+ alg3 {
+ alg-name = "alg3";
+ num-core = <28 28 15 13>;
+ status = "ok";
+ };
+ };
};
ice: crypto@...8000 {
--
2.46.0
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