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Message-ID: <20241007061926.GA800@lst.de>
Date: Mon, 7 Oct 2024 08:19:26 +0200
From: Christoph Hellwig <hch@....de>
To: Tero Kristo <tero.kristo@...ux.intel.com>
Cc: linux-kernel@...r.kernel.org, axboe@...nel.dk, hch@....de,
linux-nvme@...ts.infradead.org, sagi@...mberg.me, kbusch@...nel.org
Subject: Re: [PATCH 1/1] nvme-pci: Add CPU latency pm-qos handling
> @@ -483,6 +498,27 @@ static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
> nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
> writel(nvmeq->sq_tail, nvmeq->q_db);
> nvmeq->last_sq_tail = nvmeq->sq_tail;
> +
> + /* Kick CPU latency while updating queue. */
> + dev = nvmeq->dev;
> + if (!dev || dev->cpu_latency < 0)
> + return;
> +
> + for_each_cpu(cpu, nvmeq->irq_aff_mask) {
Doing something as complex as this for every doorbell write is not
going to fly.
Even if it was I see nothing nvme-specific in the interface.
So please figure out a way to make things cheap in the I/O path
and move code to the right layers.
Also please avoid all these overly long lines.
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