lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CANAwSgS15E4-KzexTqEYd4=o3ew9GvigEjBCZ-dAUs0No_b6Hw@mail.gmail.com>
Date: Mon, 7 Oct 2024 14:39:06 +0530
From: Anand Moon <linux.amoon@...il.com>
To: Philipp Zabel <p.zabel@...gutronix.de>
Cc: Shawn Lin <shawn.lin@...k-chips.com>, Lorenzo Pieralisi <lpieralisi@...nel.org>, 
	Krzysztof WilczyƄski <kw@...ux.com>, 
	Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, Rob Herring <robh@...nel.org>, 
	Bjorn Helgaas <bhelgaas@...gle.com>, Heiko Stuebner <heiko@...ech.de>, 
	"open list:PCIE DRIVER FOR ROCKCHIP" <linux-pci@...r.kernel.org>, 
	"open list:PCIE DRIVER FOR ROCKCHIP" <linux-rockchip@...ts.infradead.org>, 
	"moderated list:ARM/Rockchip SoC support" <linux-arm-kernel@...ts.infradead.org>, 
	open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v6 RESET 2/3] PCI: rockchip: Simplify reset control
 handling by using reset_control_bulk*() function

Hi Philipp,

Thanks for your review comment.

On Mon, 7 Oct 2024 at 14:14, Philipp Zabel <p.zabel@...gutronix.de> wrote:
>
> On So, 2024-10-06 at 23:54 +0530, Anand Moon wrote:
> > Refactor the reset control handling in the Rockchip PCIe driver,
> > introducing a more robust and efficient method for assert and
> > deassert reset controller using reset_control_bulk*() API. Using the
> > reset_control_bulk APIs, the reset handling for the core clocks reset
> > unit becomes much simpler.
> >
> > Spilt the reset controller in two groups as pre the RK3399 TRM.
> > After power up, the software driver should de-assert the reset of PCIe PHY,
> > then wait the PLL locked by polling the status, if PLL
> > has locked, then can de-assert the rest reset simultaneously
> > driver need to De-assert the reset pins simultionaly.
> >
> >   PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.
> >
> > Signed-off-by: Anand Moon <linux.amoon@...il.com>
> > ---
> > V6: Add reason for the split of the RESET pins.
> > v5: Fix the De-assert reset core as per the TRM
> >     De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
> >     simultaneously.
> > v4: use dev_err_probe in error path.
> > v3: Fix typo in commit message, dropped reported by.
> > v2: Fix compilation error reported by Intel test robot
> >     fixed checkpatch warning
> > ---
> >  drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
> >  drivers/pci/controller/pcie-rockchip.h |  26 +++--
> >  2 files changed, 49 insertions(+), 128 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> > index 2777ef0cb599..87daa3288a01 100644
> > --- a/drivers/pci/controller/pcie-rockchip.c
> > +++ b/drivers/pci/controller/pcie-rockchip.c
> [...]
> > @@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
> >       if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
> >               rockchip->link_gen = 2;
> >
> > -     rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
> > -     rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
> > -     rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
> > -     rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
> > -     rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
> > +     err = devm_reset_control_bulk_get_optional_exclusive(dev,
> [...]
>
>
> Why are the reset controls optional now? The commit message doesn't
> mention this change.
>

Oops, It should be  devm_reset_control_bulk_get_exclusive(),
I will update this in the next version.

> regards
> Philipp

Thanks
-Anand

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ