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Message-ID: <20241007100749.6657-1-macpaul.lin@mediatek.com>
Date: Mon, 7 Oct 2024 18:07:49 +0800
From: Macpaul Lin <macpaul.lin@...iatek.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Matthias Brugger
<matthias.bgg@...il.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>, Jieyy Yang <jieyy.yang@...iatek.com>,
Jian Yang <jian.yang@...iatek.com>, Jianguo Zhang
<jianguo.zhang@...iatek.com>, Alexandre Mergnat <amergnat@...libre.com>
CC: Bear Wang <bear.wang@...iatek.com>, Pablo Sun <pablo.sun@...iatek.com>,
Macpaul Lin <macpaul.lin@...iatek.com>, Macpaul Lin <macpaul@...il.com>, Sen
Chu <sen.chu@...iatek.com>, Chris-qj chen <chris-qj.chen@...iatek.com>,
MediaTek Chromebook Upstream
<Project_Global_Chrome_Upstream_Group@...iatek.com>, Chen-Yu Tsai
<wenst@...omium.org>
Subject: [PATCH] arm64: dts: mediatek: mt8390-genio-700-evk: enable pcie
Enable PCIE, PCIEPHY and related Pinctrls for mt8390-genio-700-evk
board.
Signed-off-by: Macpaul Lin <macpaul.lin@...iatek.com>
---
.../dts/mediatek/mt8390-genio-700-evk.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
Changes for v1:
- This patch depends on the pcie patch of mt8188.dtsi
[1] https://lore.kernel.org/all/20241004081218.55962-3-fshao@chromium.org/
diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
index 3e77f59f2c74..bb68665f0b2d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
@@ -393,6 +393,16 @@ &mt6359codec {
mediatek,mic-type-1 = <3>; /* DCC */
};
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins_default>;
+ status = "okay";
+};
+
+&pciephy {
+ status = "okay";
+};
+
&pio {
audio_default_pins: audio-default-pins {
pins-cmd-dat {
@@ -758,6 +768,15 @@ pins-rst {
};
};
+ pcie_pins_default: pcie-default {
+ mux {
+ pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
+ <PINMUX_GPIO48__FUNC_O_PERSTN>,
+ <PINMUX_GPIO49__FUNC_B1_CLKREQN>;
+ bias-pull-up;
+ };
+ };
+
rt1715_int_pins: rt1715-int-pins {
pins_cmd0_dat {
pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>;
--
2.45.2
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