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Message-ID: <1728491303-1456171-1-git-send-email-radhey.shyam.pandey@amd.com>
Date: Wed, 9 Oct 2024 21:58:20 +0530
From: Radhey Shyam Pandey <radhey.shyam.pandey@....com>
To: <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
	<pabeni@...hat.com>, <robh@...nel.org>, <krzk+dt@...nel.org>,
	<conor+dt@...nel.org>, <michal.simek@....com>, <harini.katakam@....com>
CC: <netdev@...r.kernel.org>, <devicetree@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
	<git@....com>, Radhey Shyam Pandey <radhey.shyam.pandey@....com>
Subject: [PATCH net-next v3 0/3] net: xilinx: emaclite: Adopt clock support

This patchset adds emaclite clock support. AXI Ethernet Lite IP can also
be used on SoC platforms like Zynq UltraScale+ MPSoC which combines
powerful processing system (PS) and user-programmable logic (PL) into
the same device. On these platforms it is mandatory to explicitly enable
IP clocks for proper functionality.

Changes for v3:
- Add Conor's ack to 1/3 patch.
- Remove braces around dev_err_probe().

Changes for v2:
- Make clocks as required property.

Abin Joseph (3):
  dt-bindings: net: emaclite: Add clock support
  net: emaclite: Replace alloc_etherdev() with devm_alloc_etherdev()
  net: emaclite: Adopt clock support

 .../bindings/net/xlnx,emaclite.yaml           |  5 +++++
 drivers/net/ethernet/xilinx/xilinx_emaclite.c | 21 ++++++++++---------
 2 files changed, 16 insertions(+), 10 deletions(-)


base-commit: 6607c17c6c5e029da03a90085db22daf518232bf
-- 
2.34.1


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