linux-kernel - Re: [PATCH V2] x86/apic: Stop the TSC Deadline timer during lapic timer shutdown

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Message-ID: <f568dbbc-ac60-4c25-80d1-87e424bd649c@intel.com>
Date: Wed, 9 Oct 2024 10:47:19 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: Zhang Rui <rui.zhang@...el.com>, tglx@...utronix.de, mingo@...hat.com,
 bp@...en8.de, dave.hansen@...ux.intel.com, rafael.j.wysocki@...el.com,
 x86@...nel.org, linux-pm@...r.kernel.org
Cc: hpa@...or.com, peterz@...radead.org, thorsten.blum@...lux.com,
 yuntao.wang@...ux.dev, tony.luck@...el.com, len.brown@...el.com,
 srinivas.pandruvada@...el.com, linux-kernel@...r.kernel.org,
 stable@...r.kernel.org
Subject: Re: [PATCH V2] x86/apic: Stop the TSC Deadline timer during lapic
 timer shutdown

On 10/9/24 00:20, Zhang Rui wrote:
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index 6513c53c9459..d1006531729a 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -441,6 +441,10 @@ static int lapic_timer_shutdown(struct clock_event_device *evt)
>  	v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
>  	apic_write(APIC_LVTT, v);
>  	apic_write(APIC_TMICT, 0);
> +
> +	if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
> +		wrmsrl(MSR_IA32_TSC_DEADLINE, 0);

One last thing, and this is a super nit.  We presumably have the actual
APIC_LVTT value (v) sitting in a register already.  Is there any
difference logically between a X86_FEATURE_TSC_DEADLINE_TIMER check and
an APIC_LVTT check for APIC_LVT_TIMER_TSCDEADLINE?

I suspect this will generate more compact code:

	if (v & APIC_LVT_TIMER_TSCDEADLINE)
		wrmsrl(MSR_IA32_TSC_DEADLINE, 0);

Does it have any downsides?

Oh, and how hot is this path?  Is this wrmsr() going to matter?  I
presume it's pretty cheap because it's one of the special
architecturally non-serializing WRMSRs.