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Message-ID: <20241009080052.GA16711@lst.de>
Date: Wed, 9 Oct 2024 10:00:52 +0200
From: Christoph Hellwig <hch@....de>
To: Tero Kristo <tero.kristo@...ux.intel.com>
Cc: Christoph Hellwig <hch@....de>, linux-kernel@...r.kernel.org,
axboe@...nel.dk, linux-nvme@...ts.infradead.org, sagi@...mberg.me,
kbusch@...nel.org
Subject: Re: [PATCH 1/1] nvme-pci: Add CPU latency pm-qos handling
On Wed, Oct 09, 2024 at 09:45:07AM +0300, Tero Kristo wrote:
> Initially, I posted the patch against block layer, but there the
> recommendation was to move this closer to the HW; i.e. NVMe driver
> level.
Even if it is called from NVMe, at lot of the code is not nvme specific.
Some of it appears block specific and other pats are entirely generic.
But I still don't see how walking cpumasks and updating paramters in
far away (in terms of cache lines and pointer dereferences) for every
single I/O could work without having a huge performance impact.
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