linux-kernel - Re: [PATCH v2 00/19] iommufd: Add VIOMMU infrastructure (Part-1)

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20241009123115.GG1365916@nvidia.com>
Date: Wed, 9 Oct 2024 09:31:15 -0300
From: Jason Gunthorpe <jgg@...dia.com>
To: Yi Liu <yi.l.liu@...el.com>
Cc: Nicolin Chen <nicolinc@...dia.com>, kevin.tian@...el.com,
	will@...nel.org, joro@...tes.org, suravee.suthikulpanit@....com,
	robin.murphy@....com, dwmw2@...radead.org, baolu.lu@...ux.intel.com,
	shuah@...nel.org, linux-kernel@...r.kernel.org,
	iommu@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
	linux-kselftest@...r.kernel.org, eric.auger@...hat.com,
	jean-philippe@...aro.org, mdf@...nel.org, mshavit@...gle.com,
	shameerali.kolothum.thodi@...wei.com, smostafa@...gle.com
Subject: Re: [PATCH v2 00/19] iommufd: Add VIOMMU infrastructure (Part-1)

On Wed, Oct 09, 2024 at 03:20:57PM +0800, Yi Liu wrote:
> On 2024/10/1 05:59, Nicolin Chen wrote:
> > On Sun, Sep 29, 2024 at 03:16:55PM +0800, Yi Liu wrote:
> > > > > > I feel these two might act somehow similarly to the two DIDs
> > > > > > during nested translations?
> > > > > 
> > > > > not quite the same. Is it possible that the ASID is the same for stage-1?
> > > > > Intel VT-d side can have the pasid to be the same. Like the gIOVA, all
> > > > > devices use the same ridpasid. Like the scenario I replied to Baolu[1],
> > > > > do er choose to use different DIDs to differentiate the caches for the
> > > > > two devices.
> > > > 
> > > > On ARM, each S1 domain (either a normal stage-1 PASID=0 domain or
> > > > an SVA PASID>0 domain) has a unique ASID.
> > > 
> > > I see. Looks like ASID is not the PASID.
> > 
> > It's not. PASID is called Substream ID in SMMU term. It's used to
> > index the PASID table. For cache invalidations, a PASID (ssid) is
> > for ATC (dev cache) or PASID table entry invalidation only.
> 
> sure. Is there any relationship between PASID and ASID? Per the below
> link, ASID is used to tag the TLB entries of an application. So it's
> used in the SVA case. right?

Unlike Intel and AMD the IOTLB tag is entirely controlled by
software. So the HW will lookup the PASID and retrieve an ASID, then
use that as a cache tag.

Intel and AMD will use the PASID as the cache tag.

As we've talked about several times using the PASID directly as a
cache tag robs the SW of optimization possibilities in some cases.

The extra ASID indirection allows the SW to always tag the same page
table top pointer with the same ASID regardless of what PASID it is
assigned to and guarentee IOTLB sharing.

Jason