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Message-ID: <79991a6f-6071-8f25-5539-8237dd612e1f@amd.com>
Date: Fri, 11 Oct 2024 15:53:05 -0500
From: "Moger, Babu" <bmoger@....com>
To: Tony Luck <tony.luck@...el.com>, Babu Moger <babu.moger@....com>
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Subject: Re: [PATCH v8 06/25] x86/resctrl: Add support to enable/disable AMD
ABMC feature
Hi Tony,
On 10/11/2024 1:14 PM, Tony Luck wrote:
> On Wed, Oct 09, 2024 at 12:39:31PM -0500, Babu Moger wrote:
>> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
>> index 3ae84c3b8e6d..43c9dc473aba 100644
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -1195,6 +1195,7 @@
>> #define MSR_IA32_MBA_BW_BASE 0xc0000200
>> #define MSR_IA32_SMBA_BW_BASE 0xc0000280
>> #define MSR_IA32_EVT_CFG_BASE 0xc0000400
>> +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff
>
> Nitpick. Most of the MSRs in this file are in numerical order (within
> each functional grouping). So this belongs before MSR_IA32_EVT_CFG_BASE
>
> Same in patch 14 which adds MSR_IA32_L3_QOS_ABMC_CFG
Yes. Will take care of this in next revision.
--
- Babu Moger
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