linux-kernel - Re: [PATCH v3 09/11] PCI: brcmstb: Adjust PHY PLL setup to use a 54MHz input refclk

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Message-ID: <60de2ae5-af4b-4c31-bc63-9f62b08be2fc@broadcom.com>
Date: Mon, 14 Oct 2024 10:07:53 -0700
From: Florian Fainelli <florian.fainelli@...adcom.com>
To: Stanimir Varbanov <svarbanov@...e.de>, linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-rpi-kernel@...ts.infradead.org, linux-pci@...r.kernel.org,
 Broadcom internal kernel review list <bcm-kernel-feedback-list@...adcom.com>
Cc: Thomas Gleixner <tglx@...utronix.de>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Jim Quinlan <jim2101024@...il.com>,
 Nicolas Saenz Julienne <nsaenz@...nel.org>,
 Bjorn Helgaas <bhelgaas@...gle.com>,
 Lorenzo Pieralisi <lpieralisi@...nel.org>, kw@...ux.com,
 Philipp Zabel <p.zabel@...gutronix.de>,
 Andrea della Porta <andrea.porta@...e.com>,
 Phil Elwell <phil@...pberrypi.com>, Jonathan Bell <jonathan@...pberrypi.com>
Subject: Re: [PATCH v3 09/11] PCI: brcmstb: Adjust PHY PLL setup to use a
 54MHz input refclk

On 10/14/24 06:07, Stanimir Varbanov wrote:
> Use canned MDIO writes from Broadcom that switch the ref_clk output
> pair to run from the internal fractional PLL, and set the internal
> PLL to expect a 54MHz input reference clock.
> 
> Without this RPi5 PCIe cannot enumerate endpoint devices on
> extension connector.

You could say that the default reference clock for the PLL is 100MHz, 
except for some devices, where it is 54MHz, like 2712d0. AFAIR, 2712c1 
might have been 100MHz as well, so whether we need to support that 
revision of the chip or not might be TBD.

> 
> Signed-off-by: Stanimir Varbanov <svarbanov@...e.de>
> ---
> v2 -> v3:
>   - New patch.
> 
>   drivers/pci/controller/pcie-brcmstb.c | 35 +++++++++++++++++++++++++++
>   1 file changed, 35 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index 407343a30439..12591e292c0c 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -55,6 +55,10 @@
>   #define PCIE_RC_DL_MDIO_WR_DATA				0x1104
>   #define PCIE_RC_DL_MDIO_RD_DATA				0x1108
>   
> +#define PCIE_RC_PL_PHY_CTL_15				0x184c
> +#define  PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK		0x400000
> +#define  PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK	0xff
> +
>   #define PCIE_MISC_MISC_CTRL				0x4008
>   #define  PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK	0x80
>   #define  PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK	0x400
> @@ -251,6 +255,7 @@ struct pcie_cfg_data {
>   	u8 num_inbound_wins;
>   	int (*perst_set)(struct brcm_pcie *pcie, u32 val);
>   	int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
> +	int (*post_setup)(struct brcm_pcie *pcie);
>   };
>   
>   struct subdev_regulators {
> @@ -826,6 +831,32 @@ static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
>   	return 0;
>   }
>   
> +static int brcm_pcie_post_setup_bcm2712(struct brcm_pcie *pcie)
> +{
> +	const u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 };
> +	const u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e };
> +	u32 tmp;
> +	int i;
> +
> +	/* Allow a 54MHz (xosc) refclk source */
> +

This newline is not necessary. Other than that:

Reviewed-by: Florian Fainelli <florian.fainelli@...adcom.com>
-- 
Florian