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Message-ID: <20241014194825.44406-2-danila@jiaxyga.com>
Date: Mon, 14 Oct 2024 22:48:25 +0300
From: Danila Tikhonov <danila@...xyga.com>
To: andersson@...nel.org,
konradybcio@...nel.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
fekz115@...il.com
Cc: cros-qcom-dts-watchers@...omium.org,
linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Danila Tikhonov <danila@...xyga.com>,
Konrad Dybcio <konrad.dybcio@...aro.org>
Subject: [RESEND PATCH v2 1/1] arm64: dts: qcom: sc7280: Add 0x81 Adreno speed bin
From: Eugene Lepshy <fekz115@...il.com>
A642L (speedbin 0x81) uses index 4, so this commit sets the fourth bit
for A642L supported opps.
Signed-off-by: Eugene Lepshy <fekz115@...il.com>
Signed-off-by: Danila Tikhonov <danila@...xyga.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index b41230651def..7c75340b3a46 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2841,14 +2841,14 @@ opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <1804000>;
- opp-supported-hw = <0x07>;
+ opp-supported-hw = <0x17>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <4068000>;
- opp-supported-hw = <0x07>;
+ opp-supported-hw = <0x17>;
};
/* Only applicable for SKUs which has 550Mhz as Fmax */
@@ -2863,14 +2863,14 @@ opp-550000000-1 {
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <6832000>;
- opp-supported-hw = <0x06>;
+ opp-supported-hw = <0x16>;
};
opp-608000000 {
opp-hz = /bits/ 64 <608000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <8368000>;
- opp-supported-hw = <0x06>;
+ opp-supported-hw = <0x16>;
};
opp-700000000 {
--
2.47.0
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